Patents by Inventor Abhiram Prabahkar
Abhiram Prabahkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230231579Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: ApplicationFiled: March 16, 2023Publication date: July 20, 2023Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
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Patent number: 11611359Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: GrantFiled: August 7, 2020Date of Patent: March 21, 2023Assignee: SK hynix Inc.Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
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Patent number: 11515897Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: GrantFiled: August 7, 2020Date of Patent: November 29, 2022Assignee: SK hynix Inc.Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
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Patent number: 11177835Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: GrantFiled: August 23, 2019Date of Patent: November 16, 2021Assignee: SK hynix Inc.Inventors: Kyoung Lae Cho, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
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Publication number: 20200373944Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: ApplicationFiled: August 7, 2020Publication date: November 26, 2020Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chengrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
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Publication number: 20200373943Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: ApplicationFiled: August 7, 2020Publication date: November 26, 2020Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chengrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
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Publication number: 20190379405Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.Type: ApplicationFiled: August 23, 2019Publication date: December 12, 2019Inventors: Kyoung Lae CHO, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
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Patent number: 10419024Abstract: Techniques for improving the latency or processing performance of an error correction system are described. In an example, the error correction system implements LDPC decoding and uses an early termination rule to determine whether the LDPC decoding should be terminated prior to reaching a maximum number of iterations. The early termination rule involves various parameters that relate to the syndrome of the decoded LDPC codeword at each iteration. These parameters include the number of the current decoding iteration and the weight of the syndrome at the current iteration. For example, the early termination rule specifies that the LDPC decoding should be terminated prior to the maximum number of iterations either when the weight of the syndrome is zero, or when the current number of iterations reaches an iteration number threshold and the weight of the syndrome equals or exceeds a checksum threshold.Type: GrantFiled: May 26, 2017Date of Patent: September 17, 2019Assignee: SK Hynix Inc.Inventors: Chenrong Xiong, Fan Zhang, Yu Cai, Aman Bhatia, Naveen Kumar, Abhiram Prabahkar
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Publication number: 20180343082Abstract: Techniques for improving the latency or processing performance of an error correction system are described. In an example, the error correction system implements LDPC decoding and uses an early termination rule to determine whether the LDPC decoding should be terminated prior to reaching a maximum number of iterations. The early termination rule involves various parameters that relate to the syndrome of the decoded LDPC codeword at each iteration. These parameters include the number of the current decoding iteration and the weight of the syndrome at the current iteration. For example, the early termination rule specifies that the LDPC decoding should be terminated prior to the maximum number of iterations either when the weight of the syndrome is zero, or when the current number of iterations reaches an iteration number threshold and the weight of the syndrome equals or exceeds a checksum threshold.Type: ApplicationFiled: May 26, 2017Publication date: November 29, 2018Inventors: Chenrong Xiong, Fan Zhang, Yu Cai, Aman Bhatia, Naveen Kumar, Abhiram Prabahkar