Abstract: Memory controllers, decoders and methods execute a hybrid decoding scheme. An initial iteration of decoding of a codeword is performed using a bit-flipping (BF) decoder or a min-sum (MS) decoder depending on whether or not an unsatisfied check (USC) count of the codeword is less than a threshold. For this initial iteration, the BF decoder is used when the USC count is less than the threshold, and MS decoder when the USC count is greater than or equal to the threshold. When decoding of the codeword is initially performed with the BF decoder, decoding continues with the BF decoder until a first set of conditions is satisfied or the codeword is successfully decoded. When decoding of the codeword is performed with the MS decoder, decoding continues with the MS decoder until a second set of conditions is satisfied.

Abstract: A low density parity check (LDPC) decoding device includes a data generator for generating information with a first precision; a data converter for converting the information into a message with a second precision greater than the first precision; and a decoding processor for performing a low density parity check (LDPC) decoding using the message to generate decoded data.

Abstract: Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a min-sum decoding approach that monitors whether two values received in messages from two variable nodes connected to a check nodes are equal and are the minimum value among the values received by the check nodes from other variable nodes connected thereto. Upon detecting such an event, the minimum value is adjusted by reducing it by an adjustment value to generate an adjusted minimum value. This adjusted minimum value approximates the minimum value that a sum-product algorithm (SPA) decoding approach would have generated. The adjusted minimum value is included in a response message sent from the check node to a variable node. The bit corresponding to that variable node is decoded based on this adjusted minimum value.

Abstract: A memory system with a shared buffer architecture for multiple decoders reduces transfer latency and power consumption. Such memory system includes a memory device to generate codewords, and a dynamic memory access (DMA) assembly to receive the generated codewords. A first decoding stage of the system comprises a checksum module and a shared memory buffer, including a memory manager and destination ports, that stores and manages codewords received from the DMA assembly. A second decoding stage of the system comprises a bit-flipping (BF) decoder and a min-sum (MS) decoder, each in communication with the shared memory buffer through a respective one of the destination ports. In managing the codewords stored in the shared memory buffer, the memory manager controls assignment including reassignment of the codewords among the destination ports.

Abstract: Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.

Abstract: Memory controllers, decoders and methods execute a hybrid decoding scheme. An initial iteration of decoding of a codeword is performed using a bit-flipping (BF) decoder or a min-sum (MS) decoder depending on whether or not an unsatisfied check (USC) count of the codeword is less than a threshold. For this initial iteration, the BF decoder is used when the USC count is less than the threshold, and MS decoder when the USC count is greater than or equal to the threshold. When decoding of the codeword is initially performed with the BF decoder, decoding continues with the BF decoder until a first set of conditions is satisfied or the codeword is successfully decoded. When decoding of the codeword is performed with the MS decoder, decoding continues with the MS decoder until a second set of conditions is satisfied.

Abstract: A low density parity check (LDPC) decoding device includes a data generator for generating information with a first precision; a data converter for converting the information into a message with a second precision greater than the first precision; and a decoding processor for performing a low density parity check (LDPC) decoding using the message to generate decoded data.

Abstract: Techniques are described for encoding information data bits using a low-density parity-check matrix optimized for a Low-Density Parity-Check (LDPC) encoder. In an example, the parity-check matrix includes a first matrix and a second matrix. The second matrix is a square matrix, and is also a block diagonal matrix that includes a set of square submatrices located on the diagonal of the block diagonal matrix. An intermediate vector is generated based on the information data bits and the first matrix, and a parity vector of a codeword is generated based on the intermediate vector and the second matrix.

Abstract: Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a min-sum decoding approach that monitors whether two values received in messages from two variable nodes connected to a check nodes are equal and are the minimum value among the values received by the check nodes from other variable nodes connected thereto. Upon detecting such an event, the minimum value is adjusted by reducing it by an adjustment value to generate an adjusted minimum value. This adjusted minimum value approximates the minimum value that a sum-product algorithm (SPA) decoding approach would have generated. The adjusted minimum value is included in a response message sent from the check node to a variable node. The bit corresponding to that variable node is decoded based on this adjusted minimum value.

Abstract: Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.

Abstract: A memory system with a shared buffer architecture for multiple decoders reduces transfer latency and power consumption. Such memory system includes a memory device to generate codewords, and a dynamic memory access (DMA) assembly to receive the generated codewords. A first decoding stage of the system comprises a checksum module and a shared memory buffer, including a memory manager and destination ports, that stores and manages codewords received from the DMA assembly. A second decoding stage of the system comprises a bit-flipping (BF) decoder and a min-sum (MS) decoder, each in communication with the shared memory buffer through a respective one of the destination ports. In managing the codewords stored in the shared memory buffer, the memory manager controls assignment including reassignment of the codewords among the destination ports.

Abstract: Techniques are described for encoding information data bits using a low-density parity-check matrix optimized for a Low-Density Parity-Check (LDPC) encoder. In an example, the parity-check matrix includes a first matrix and a second matrix. The second matrix is a square matrix, and is also a block diagonal matrix that includes a set of square submatrices located on the diagonal of the block diagonal matrix. An intermediate vector is generated based on the information data bits and the first matrix, and a parity vector of a codeword is generated based on the intermediate vector and the second matrix.

Abstract: Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.

Abstract: Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch memory and a checksum update unit, the LDPC decoder suitable for, during the first decoding iteration, storing the Lch sign values in the Lch memory of the LDPC decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.

Abstract: Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.

Abstract: Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits.

Abstract: Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits.

Abstract: Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch memory and a checksum update unit, the LDPC decoder suitable for, during the first decoding iteration, storing the Lch sign values in the Lch memory of the LDPC decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.

Abstract: Decoding an LDPC encoded codeword is disclosed. Variable nodes corresponding to a parity check matrix of the LDPC encoded codeword have been divided into a plurality of groups. A selected group of variable nodes from the plurality of groups of variable nodes is updated. Check nodes are updated using a min-sum update. A selected input value provided from a variable node of the selected group of variable nodes and provided to a certain check node of the check nodes is discarded to be not available for use in a future min-sum update.

Abstract: A hinge path is used to determine if a first possible root is a root of an error location polynomial. A positive limb path is used to determine if a second possible root is a root of the error location polynomial, including by using a sequence of coefficients associated with the error location polynomial. The sequence of coefficients is reversed and a negative limb path is used to determine if a third possible root is a root of the error location polynomial, including by using the reversed sequence of coefficients, wherein the negative limb path is a copy of the positive limb path.