Abstract: In one embodiment, the invention comprises: defining a first volume in a layer of a semiconductor device; calculating a probability of finding at least one dopant atom in the first volume, based on a dopant distribution of the layer; in the case that the calculated probability is equal to or greater than a pre-determined threshold, defining at least one additional volume in the layer substantially equal to the first volume; and in the case that the calculated probability is less than the pre-determined threshold: aggregating the first volume with a second volume adjacent the first volume, the second volume being substantially equal to the first volume; and recalculating a probability of finding at least one dopant atom in the aggregated first and second volumes, based on the dopant distribution of the layer.

Abstract: In one embodiment, the invention comprises: defining a first volume in a layer of a semiconductor device; calculating a probability of finding at least one dopant atom in the first volume, based on a dopant distribution of the layer; in the case that the calculated probability is equal to or greater than a pre-determined threshold, defining at least one additional volume in the layer substantially equal to the first volume; and in the case that the calculated probability is less than the pre-determined threshold: aggregating the first volume with a second volume adjacent the first volume, the second volume being substantially equal to the first volume; and recalculating a probability of finding at least one dopant atom in the aggregated first and second volumes, based on the dopant distribution of the layer.

Abstract: Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.

Abstract: Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.

Abstract: A CMOS inverter formed with narrowly spaced fins structures including transistors formed on sidewalls of each fin structure. A high-k dielectric material is deposited on the fins to provide mechanical stability to the fins and serve as a gate dielectric material. A mid gap metal gate layer may be formed on the high-k dielectric layer.

Abstract: A CMOS inverter formed with narrowly spaced fins structures including transistors formed on sidewalls of each fin structure. A high-k dielectric material is deposited on the fins to provide mechanical stability to the fins and serve as a gate dielectric material. A mid gap metal gate layer may be formed on the high-k dielectric layer.

Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.

Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.