Abstract: A thin film transistor (TFT) apparatus is disclosed, where the apparatus includes a gate comprising metal, a source and a drain, a semiconductor body, and two or more dielectric structures between the gate and the semiconductor body. In an example, the two or more dielectric structures may include at least a first dielectric structure having a first bandgap and a second dielectric structure having a second bandgap. The first bandgap may be different from the second bandgap. The TFT apparatus may be a back-gated TFT apparatus where the source is at least in part coplanar with the drain, and the gate is non-coplanar with the source and the drain.

Abstract: A method for identifying and managing incidents in a building management system (BMS) of a building. The method includes identifying at least one or more entities, one or more intents, or one or more keywords from a text segment; extracting one or more parameters from at least one of the identified one or more entities, the identified one or more intents, or the identified one or more keywords, the one or more parameters comprising a piece of building equipment of the building and a characteristic of the piece of building equipment; determining a satisfied incident of a plurality of incidents based on the extracted one or more parameters, the satisfied incident identifying an issue with the piece of building equipment and associated with a second entity; and transmitting an indication of the satisfied incident to a computing device of the second entity.

Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.

Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.

Abstract: A system for detecting a road surface includes a computer programmed to determine a virtual boundary for a vehicle body based on a shape of the vehicle body, upon identifying an object, to identify a plurality of points on the object based on received sensor data, to determine a barrier function based on each of the identified plurality of points, wherein the barrier function includes a barrier distance from a reference point of the virtual boundary of the vehicle to a respective one of the points on the object, based on (i) the determined barrier functions, (ii) the determined virtual boundary of the vehicle, and (iii) an input to at least one of propulsion, steering, or braking, to determine at least one of a braking override or a steering override, and based on the determination, to adjust at least one of a vehicle steering or a vehicle speed.

Abstract: A system for detecting a road surface includes a processor and a memory. The memory stores instructions executable by the processor to determine a virtual boundary for a vehicle body based on a shape of the vehicle body, to identify one or more objects based on vehicle sensor data, based on the identified one or more objects, the determined virtual boundary, and an input to at least one of propulsion, steering, or braking, to determine at least one of a braking override or a steering override, and based on the determination, to perform at least one of adjusting a vehicle steering and a vehicle speed.

Abstract: Automated patient positioning and modelling includes a hardware processor to obtain image data from an imaging sensor, classify the image data, using a first machine learning model, as a patient pose based on one or more pre-defined protocols for patient positioning, provide a confidence score based on the classification of the image data and if the confidence score is less than a pre-determined value, re-classify the image data using a second machine learning model; or if the confidence score is greater than a pre-determined value, identify the image data as corresponding to a patient pose based on one or more pre-defined protocols for patient positioning during a scan procedure.

Abstract: A stacked-substrate advanced encryption standard (AES) integrated circuit device is described in which at least some circuits associated logic functions (e.g., AES encryption operations, memory cell access and control) are provided on a first substrate. Memory arrays used with the AES integrated circuit device (sometimes referred to as “embedded memory”) are provided on a second substrate stacked on the first substrate, thus forming a AES integrated circuit device on a stacked-substrate assembly. Vias are fabricated to pass through the second substrate, into a dielectric layer between the first substrate and the second substrate, and electrically connect to conductive interconnections of the AES logic circuits.

Abstract: Provided is a method, performed by an information processing device, of processing information by using an Internet of things (IoT) device, the method including: receiving, from a user, a web search query; fetching context information of at least one IoT device related to the web search query; automatically generating a synthetic web search query including the web search query and the context information of the at least one IoT device; and determining a control to be applied to the at least one IoT device by using a search result regarding the synthetic web search query.

Abstract: Embodiments include a transistor device that comprises a gate electrode and a gate dielectric surrounding the gate electrode. In an embodiment, a source region may be below the gate electrode and a drain region may be above the gate electrode. In an embodiment, a channel region may be between the source region and the drain region. In an embodiment, the channel region is separated from a sidewall of the gate electrode by the gate dielectric. In an embodiment, a capacitor may be electrically coupled to the drain region.

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

Abstract: A technique implements a dataflow graph, taking a number of streams of data inputs and transforms these inputs into a number of streams of outputs. The dataflow graph can perform pattern matching. The technique implements reactions via the composition of pattern matching across joined streams of input data. A completeness of matching an input sequence to a particular input pattern can be characterized as having at least three different degrees, such as cold (not yet matched), warm (e.g., minimally matched), and hot (e.g., maximally matched). The input pattern to be matched can have a variable length, including zero length or unlimited or arbitrarily large length. Data flows can be on a push basis or pull basis, or a combination, and may change depending on the state.

Abstract: Systems, methods and instrumentalities are described herein for automating a medical environment. The automation may be realized using one or more sensing devices and at least one processing device. The sensing devices may be configured to capture images of the medical environment and provide the images to the processing device. The processing device may determine characteristics of the medical environment based on the images and automate one or more aspects of the operations in the medical environment. These characteristics may include, e.g., people and/or objects present in the images and respective locations of the people and/or objects in the medical environment. The operations that may be automated may include, e.g., maneuvering and/or positioning a medical device based on the location of a patient, determining and/or adjusting the parameters of a medical device, managing a workflow, providing instructions and/or alerts to a patient or a physician, etc.

Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

Abstract: Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

Abstract: Embodiments of the present disclosure relate to methods of fabricating IC devices with IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure, as well as resulting IC devices, assemblies, and systems. An example method includes providing a semiconductor material over a semiconductor support structure and, subsequently, depositing a first bonding material on the semiconductor material. The method further includes depositing a second bonding material on a non-semiconductor support structure such as glass or mica wafers, followed by bonding the face of the semiconductor material with the first bonding material to the face of the non-semiconductor support structure with the second bonding material. Using first and second bonding materials that include silicon, nitrogen, and oxygen (e.g.

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

Abstract: A memory cell is disclosed. The memory cell includes a storage component that includes a chalcogenide stack that includes a plurality of layers of material and a selector component that includes a Schottky diode.

Abstract: A method includes processing event data to detect a status of a network function. The event data is processed based on two or more conditions defined by a correlation policy. The correlation policy includes a non-deterministic finite automata tree (NFAT) structure correlation policy having a policy type and a logic-gate. The method additionally includes determining the policy type of the NFAT structure correlation policy. The method also includes determining whether a first value of the two or more conditions is indicative of whether a first condition is satisfied. The method further includes determining whether a second value of the two or more conditions is indicative of whether the second condition is satisfied. The method additionally includes determining whether the NFAT structure correlation policy is satisfied based on the first value, the second value, the logic-gate and the policy type.

Abstract: Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.