Patents by Inventor Abhishek Bansal

Abhishek Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10733659
    Abstract: Embodiments of the present invention are directed to systems and methods for generating, receiving and processing product-specific network addresses that may be used to generate product-specific checkout pages. In some embodiments, an intermediary server is provided that generates product-specific network addresses for merchants to be used on media websites. The product-specific network address is stored by the intermediary server in association with particular product information. The intermediary server acts as an interface between a user that visits the product-specific network address and a host checkout server. Specifically, the intermediary server receives the product-specific network address, retrieves the associated product information, and forwards the product information to the host checkout server. The host checkout server may then generate a checkout page for the user using the product information.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 4, 2020
    Assignee: Visa International Service Association
    Inventors: Zeeshanul Haque, Abhishek Bansal
  • Publication number: 20200167159
    Abstract: A process for processor testing includes dividing a memory space into first and second portions and generating first and second sets of test instructions for the respective first and second portion. The first and second sets each include a plurality of counter increment/branch instruction pairs where each branch instruction of the first set branches to a backward instruction location and each branch instruction of the second set branches to a forward instruction location.
    Type: Application
    Filed: January 29, 2020
    Publication date: May 28, 2020
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Publication number: 20200160271
    Abstract: A computer implemented method includes collecting collaboration information containing data representative of collaborations between at least two individuals, applying time allocation heuristics to the collected collaboration data to extract respective collaborations times for the at least two individuals, storing the extracted collaborations times on a storage device, and accessing the storage device to process queries regarding collaboration between the at least two individuals.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 21, 2020
    Inventors: Chantrelle Nielsen, Nikolay Mitev Trandev, Brett Daniel Mills, Dheepak Ramaswamy, Si Meng, Zoey Jennifer Geary, Mugdha Kolhatkar, Pracheer Agarwal, Shubham Aggarwal, Tapas Bansal, Siddarth Rejendra Kumar, Abhishek Kalai Raghavendra, Jagadeesh Huliyar, Sanjay H. Ramaswamy, Sai Sumana Pagidipalli, Shubham Aggarwal, Sreeram Nivarthi
  • Publication number: 20200092271
    Abstract: The disclosed system implements techniques to secure communications for injecting a workload (e.g., a container) into a virtual network hosted by a cloud-based platform. Based on a delegation instruction received from a tenant, a virtual network of the tenant can connect to and execute a workload via a virtual machine that is part of a virtual network that belongs to a resource provider. To secure calls and authorize access to the tenant's virtual network, authentication information provided in association with a call from the virtual network of the resource provider may need to match authorization information made available via a publication service of the cloud-based platform. Moreover, an identifier of a NIC used to make a call may need to correspond to a registered name of the resource provider for the call to be authorized. These checks provide increased security by preventing unauthorized calls from accessing the tenant's virtual network.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 19, 2020
    Inventors: Abhijeet KUMAR, Aanand RAMACHANDRAN, Jayesh KUMARAN, David Michael BRUMLEY, Rishabh TEWARI, Nisheeth SRIVASTAVA, Sushant SHARMA, Deepak BANSAL, Abhishek Ellore SREENATH, Parag SHARMA, Abhishek SHUKLA, Avijit GUPTA
  • Patent number: 10585668
    Abstract: A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Patent number: 10388121
    Abstract: A method for providing notifications is provided. The method includes a tangible user interface (TUI) element the receives an input from a computing device coupled to the TUI element. The input is indicative of an outcome corresponding to a functionality of an application on the computing device. Based on the outcome, the TUI element determines at least one illumination pattern from a plurality of pre-stored illumination patterns. Thereafter, the TUI element generates an output based on the at least one determined illumination pattern.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ayushi Gupta, Prantik Banerjee, Theophilus Thomas, Kyoungwoon Hahm, Arun Prabhakar, Govind Janardhanan, Dhananjay L Govekar, Sudhanwa Suhas Chavan, Navneet Passi, Abhishek Kumar, Avinash Thakur, Nitin Setia, Suprateem Bhattacherjee, Sankara Narayanan T, Himanshu Jakhmola, Sonam Chawla, Rekha Agarwal, Atul Sharma, Aashaank Pratap, Shantanu Kumar Meher, Arungeeth PS, Amit Bansal, Kaushal Prakash Sharma, Jatin Jain
  • Patent number: 10365780
    Abstract: Techniques are disclosed for making an electronic document easier to use based on prior interactions with the same or a similar document by other users. An electronic document is presented to one or more users in an interactive environment. Interactions between the users and the document can be recorded as usage data. The usage data may represent one or more operations performed on the electronic document by the users. Based on the usage data, an enhanced user interaction feature associated with the document is configured. The electronic document and the enhanced user interaction feature are then presented to another user in another interactive environment. The enhanced user interaction feature makes using the document easier than it would be if the feature was not present, particularly for users who are unfamiliar with the document.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: July 30, 2019
    Assignee: Adobe Inc.
    Inventors: Yash Kumar Gupta, Lalit Vohra, Abhishek Modi, Aditya Kumar Pandey, Ankit Pangasa, Frederic Thevenet, Kirk B. Gould, Mohit Bansal, Nishant Kaushik, David Sherry, Steve Dakin, Vishal K. Gupta
  • Patent number: 10305640
    Abstract: Provided is a communication method of a node, including receiving a first interest requesting content from a previous node in a content centric network (CCN), generating a first acknowledgment (ACK) message indicating reception of the first interest in response to receiving the first interest, and sending the first ACK message to the previous node. Provided also is a node that includes structure that is suitable to perform such a communication method.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Abhishek Gupta, Bhargavi M. Shankarananda, Kushal Bansal
  • Publication number: 20180047087
    Abstract: Embodiments of the present invention are directed to systems and methods for generating, receiving and processing product-specific network addresses that may be used to generate product-specific checkout pages. In some embodiments, an intermediary server is provided that generates product-specific network addresses for merchants to be used on media websites. The product-specific network address is stored by the intermediary server in association with particular product information. The intermediary server acts as an interface between a user that visits the product-specific network address and a host checkout server. Specifically, the intermediary server receives the product-specific network address, retrieves the associated product information, and forwards the product information to the host checkout server. The host checkout server may then generate a checkout page for the user using the product information.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 15, 2018
    Inventors: Zeeshanul Haque, Abhishek Bansal
  • Publication number: 20180024833
    Abstract: A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Patent number: 9785439
    Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Publication number: 20150026445
    Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
    Type: Application
    Filed: September 3, 2014
    Publication date: January 22, 2015
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Patent number: 8914622
    Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Patent number: 8812826
    Abstract: In one implementation, processor testing may include the ability to randomly generate a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. Processor testing may also include the ability to randomly generate a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. Processor testing may additionally include the ability to generate a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Abhishek Bansal, Nitin Gupta, Brad L. Herold, Jayakumar N Sankarannair
  • Publication number: 20120216023
    Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Publication number: 20120102302
    Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair