Abstract: The technology disclosed herein determining one or more vulnerable instructions in workload code and determining one or more additional instructions to be inserted in the workload code based at least in part on a power model of a system bus of a processor, when a power model of a processor is dependent on an order of instructions of workload code, inserting the one or more additional instructions with dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions; and when the power model is not dependent on the order of instructions of workload code, inserting the one or more additional instructions without dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions.

Abstract: The disclosure describes techniques for enhancements to the Multicast Source Discovery Protocol (MSDP) to reduce Source Active (SA) message loops in one or more multicast domains having overlapping MSDP mesh groups. In some examples, a method includes receiving, by a first MSDP speaker, from a second MSDP speaker, a SA message. The method also includes, when the second MSDP speaker is in a mesh group with the first MSDP speaker, determining whether the first MSDP speaker includes an active SA state corresponding to the SA message. Additionally, the method includes, when the first MSDP speaker does not include the active SA state corresponding to the SA message, accepting the SA message and forwarding the SA message to a third MSDP speaker that is not in the mesh group with the first MSDP speaker and the second MSDP speaker.

Abstract: The disclosure describes techniques for enhancements to the Multicast Source Discovery Protocol (MSDP) to reduce Source Active (SA) message loops in one or more multicast domains having overlapping MSDP mesh groups. In some examples, a method includes receiving, by a first MSDP speaker, from a second MSDP speaker, a SA message. The method also includes, when the second MSDP speaker is in a mesh group with the first MSDP speaker, determining whether the first MSDP speaker includes an active SA state corresponding to the SA message. Additionally, the method includes, when the first MSDP speaker does not include the active SA state corresponding to the SA message, accepting the SA message and forwarding the SA message to a third MSDP speaker that is not in the mesh group with the first MSDP speaker and the second MSDP speaker.

Abstract: A first network device may determine that a link-state database (LSDB), associated with the first network device, includes a first link-state advertisement (LSA) instance associated with a second network device. The first network device may determine that the first network device has not received a second LSA instance, associated with the second network device, that does not include information identifying a fully adjacent link between the second network device and the first network device. The first network device may receive the second LSA instance associated with the second network device and may transmit, to the second network device, a third LSA instance, associated with the first network device, that includes the information identifying the fully adjacent link between the second network device and the first network device, only after the second LSA instance is received.

Abstract: Multiple Register State Machines on a rendezvous point router (“RP”) in a Protocol Independent Multicast-Sparse Mode (“PIM-SM”) domain per (S,G) is supported, thereby increasing the Register state consistency and faster convergence in case of a first hop router (“FHR”) failure. Such example embodiments may advantageously eliminate the limitation of a single Register State Machine on RP for a given (S,G), in the presence of multiple FHRs connected to the same source. At least some such example embodiments provide the capability of maintaining multiple Register State Machines on RP for a given (S,G), in a way, that maps one Register State Machine to each FHR. In this way, the RP can avoid the inconsistent FHR states and traffic losses caused due to FHR failures.

Abstract: A first network device detects a link down event associated with a second network device, where the link down event is detected by the first network device prior to being detected by a third network device, and the second network device is a designated network device of a network. The first network device starts a delay timer before processing the link down event, and detects an event that includes at least one of receipt, from the third network device, of a link state advertisement message based on the link down event, or an expiration of the delay timer. The first network device determines the first network device to be a new designated network device for the network based on detecting the event, and provides, to the third network device, information indicating that the first network device is the new designated network device for the network.

Abstract: The potential problem of traffic loss during a period when a second PIM router is elected DR after a first PIM router (on the same PIM interface) was previously elected DR and is transiting multicast traffic, is solved by (1) configuring a first interval on a PIM interface for at least the first PIM router; (2) responsive to the PIM interface of the first PIM router booting up, (i) starting, by the first PIM router, a timer corresponding to the configured first interval, (ii) determining, by the first PIM router, whether or not it is the DR on the PIM interface, (iii) upon determining that the timer has expired, redetermining, by the first PIM router, whether or not it is the DR on the PIM interface, and (iv) responsive to a redetermination that the first PIM router is the DR on the PIM interface, (A) increasing, by the first PIM router, a DR priority value of the first PIM router to reduce a likelihood that another of the at least two PIM routers will replace the first PIM router as DR, and (B) sending on th

Abstract: A first network device detects a link down event associated with a second network device, where the link down event is detected by the first network device prior to being detected by a third network device, and the second network device is a designated network device of a network. The first network device starts a delay timer before processing the link down event, and detects an event that includes at least one of receipt, from the third network device, of a link state advertisement message based on the link down event, or an expiration of the delay timer. The first network device determines the first network device to be a new designated network device for the network based on detecting the event, and provides, to the third network device, information indicating that the first network device is the new designated network device for the network.

Abstract: Embodiments herein relate to a master process being executed by a processor to control an upgrade to an application process. For instance, the master process initializes an environment for operating an application process and starting an execution of the application process within the environment. Further, the master process upgrades a code of the application process while the master process maintains the environment and the execution of the application process.

Abstract: Embodiments herein relate to a master process being executed by a processor to control an upgrade to an application process. For instance, the master process initializes an environment for operating an application process and starting an execution of the application process within the environment. Further, the master process upgrades a code of the application process while the master process maintains the environment and the execution of the application process.

Abstract: Embodiments herein relate to a master process being executed by a processor to control an upgrade to an application process. For instance, the master process initializes an environment for operating an application process and starting an execution of the application process within the environment. Further, the master process upgrades a code of the application process while the master process maintains the environment and the execution of the application process.

Abstract: Embodiments herein relate to a master process being executed by a processor to control an upgrade to an application process. For instance, the master process initializes an environment for operating an application process and starting an execution of the application process within the environment. Further, the master process upgrades a code of the application process while the master process maintains the environment and the execution of the application process.

Abstract: In an embodiment, a delay circuit includes a ring oscillator circuit and a counter circuit. The ring oscillator circuit includes a delay chain having delay elements and configured to generate one of more clock cycles of an oscillator clock signal in response to a clock cycle of a clock signal. The counter circuit includes two counters that are configured to store a count state corresponding to a number of clock cycles of the oscillator clock signal during a single clock cycle of the clock signal. A first buffer is configured to store the number of clock cycles of the oscillator clock signal. The delay circuit includes a buffer to store a bit pattern corresponding to a number of delay elements traversed in a partial clock cycle of the oscillator clock signal in response to the clock cycle of the clock signal based on outputs of the plurality of delay elements.

Abstract: Various embodiments of circuits and methods for enabling a slew rate programmability and compensation of input/output circuits are provided. The circuit includes a delay code generation circuit and at least one input/output (I/O) circuit. The delay code generation circuit is configured to receive a clock signal and a delay factor and generate a compensated delay code based on the clock signal or a combination of the delay factor and the clock signal. The I/O circuit includes a plurality of delay lines associated, integrated or communicatively associated with the delay code generation circuit and is configured to program the plurality of delay lines so as to generate a predetermined delay corresponding to the compensated delay code in order to achieve a predetermined slew rate of the I/O circuit.

Abstract: Proposed is the use of a document widget for representing a property of a document. The document widget comprises: a human-readable portion for interpretation by a user; and a machine-readable portion representing the document property. By comprising information about a property of a document, a document widget may be processed in accordance with an optical recognition process so as to identify the document widget and enable extraction of the document property.

Abstract: Proposed is the use of a document widget for representing a property of a document. The document widget comprises: a human-readable portion for interpretation by a user; and a machine-readable portion representing the document property. By comprising information about a property of a document, a document widget may be processed in accordance with an optical recognition process so as to identify the document widget and enable extraction of the document property.

Abstract: A method and/or system of uncompromised standard input set-up time with improved enable input set-up time characteristics in a storage circuit are disclosed. In one embodiment, a storage circuit includes a master latch coupled to a slave latch where each undergoes data transmission at an opposite transition edge of a clock cycle, an input multiplexer to apply the scan input data and/or a standard input data to the storage circuit based on a state of a scan signal, and a latch multiplexer in the master latch to apply an input multiplexer output data and a previous clock cycle output data to the storage circuit based on the state of the scan signal, a state of the enable signal, and/or a state of a current clock cycle timing signal.