Patents by Inventor Abhishek Choudhury

Abhishek Choudhury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11838432
    Abstract: A portable electronic device includes a housing defining an internal volume and a circuit board assembly within the internal volume. The circuit board assembly includes a first circuit board, a wall structure soldered to the first circuit board, and a second circuit board soldered to the wall structure and supported above the first circuit board by the wall structure. The second circuit board defines an exterior top surface of the circuit board assembly. A processor is coupled to the first circuit board and positioned within an internal volume defined between the first circuit board and the second circuit board and at least partially surrounded by the wall structure. A memory module is coupled to the exterior top surface of the circuit board assembly.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: December 5, 2023
    Assignee: APPLE INC.
    Inventors: Bryan D. Keen, Devon A. Monaco, Sherry Lee, Ihtesham H. Chowdhury, Eric N. Nyland, Matthew D. Hill, Arun R. Varma, Lucy E. Browning, Sawyer I. Cohen, Benjamin J. Pope, Abhishek Choudhury, James W. Bilanski, Yaodong Wang, Daniel J. Morizio, Nicholas W. Ruhter, David A. Karol, Sean M. Gordoni
  • Patent number: 10204876
    Abstract: A device and fabrication techniques are described that employ wafer-level packaging techniques for fabricating semiconductor devices that include a pad defined contact. In implementations, the wafer-level package device that employs the techniques of the present disclosure includes a substrate, a passivation layer, a top metal contact pad, a thin film with a via formed therein, a redistribution layer structure configured to contact the top metal contact pad, and a dielectric layer on the thin film and the redistribution layer structure. In implementations, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, forming a passivation layer, depositing a top metal contact pad, forming a thin film with a via formed therein, forming a redistribution layer structure in the via formed in the thin film, and forming a dielectric layer on the thin film and the redistribution layer structure.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 12, 2019
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Tiao Zhou, Ricky Agrawal, Abhishek Choudhury
  • Patent number: 8633601
    Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: January 21, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Nitesh Kumbhat, Abhishek Choudhury, Venkatesh V. Sundaram, Rao R. Tummala
  • Publication number: 20120104603
    Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.
    Type: Application
    Filed: July 13, 2010
    Publication date: May 3, 2012
    Applicant: Georgia Tech Research Corporation
    Inventors: Nitesh Kumbhat, Abhishek Choudhury, Venky Sundaraman, Rao R. Tummala