Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Abstract: Systems and methods for reducing routing congestion in an integrated circuit allow an integrated circuit floorplan to be modified, for example, after cell placement and global routing. Modifying the floorplan can avoid delays in time to market for the integrated circuit and can avoid increasing the size of the integrated circuit. Reducing routing congestion includes adding routing congestion reduction regions in cell/routing regions of the floorplan. The routing congestion reduction regions may modify how cells can be placed in the region. The routing congestion reduction regions may also modify how connections can be routed in the region. The routing congestion reduction regions may be a halo region that includes modifying preferred routing directions in regions nears edges of hard macros, a hammerhead region that includes laterally expanding the end of the river routing region, and a corner congestion reduction region for use at corners of hard macros.