Patents by Inventor Abhishek Kanungo

Abhishek Kanungo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hybrid deferred assertion for circuit design
    Patent number: 11023637
    Abstract: A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned to the second power domain. The logic simulation EDA application can be configured to convert, in response to user input, each SIA in the list of SIAs into a respective hybrid deferred assertion (HDA) to form a list of HDAs for the imported module and execute a simulation of the IC chip, and execution of the simulation can include execution of a plurality of time slots for a plurality of simulation cycles.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Kohli, Sulabh Nangalia, Apurva Kalia, Yonghao Chen, Mickey Rodriguez, Abhishek Kanungo
  • Method and system for providing an implicit unknown value to user ENUM data constructs in an HDL system to model power shutoff in simulation
    Patent number: 8997068
    Abstract: A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: March 31, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abhishek Kanungo, Phil Giangarra, Yonghao Chen, Franz Erich Marschner
  • Method and system for providing an implicit unknown value to user enum data constructs in an HDL system to model power shutoff in simulation
    Patent number: 8775150
    Abstract: A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: July 8, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abhishek Kanungo, Phil Giangarra, Yonghao Chen, Franz Erich Marschner
  • Methods and apparatus for merging coverage for multiple verification and design scenarios
    Patent number: 7890902
    Abstract: A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment, design and verification checksums are calculated for instances of a desired module. The design and verification checksums may be used to further derive hierarchical design and functional checksums. In another embodiment, these checksums are used to merge multiple databases produced by verification runs. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to merge multiple verification databases.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: February 15, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bijaya Sahu, Abhishek Kanungo, Sandeep Pagey, Christer Cederberg