Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access.

Abstract: A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access.