Abstract: Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

Abstract: A system includes a memory and a processor. The processor is configured to execute computer program codes to perform operations below. A netlist of a functional unit is transformed to a first matrix. The netlist includes information associated with nodes and flip-flops. A first node is selected from the nodes according to the first matrix and a second matrix, to generate a fault list. The second matrix includes weighting values for the nodes. The first node is determined to be associated with a maximum number of the flip-flops. A fault injection is performed on the functional unit. The functional unit is analyzed according to the netlist and the fault list, to generate a first file. A safety mechanism unit is analyzed to generate a second file. A failure is detected according to the first file or a combination of the first file and the second file.

Abstract: Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

Abstract: A system includes a memory and a processor. The processor is configured to execute computer program codes to perform operations below. A netlist of a functional unit is transformed to a first matrix. The netlist includes information associated with nodes and flip-flops. A first node is selected from the nodes according to the first matrix and a second matrix, to generate a fault list. The second matrix includes weighting values for the nodes. The first node is determined to be associated with a maximum number of the flip-flops. A fault injection is performed on the functional unit. The functional unit is analyzed according to the netlist and the fault list, to generate a first file. A safety mechanism unit is analyzed to generate a second file. A failure is detected according to the first file or a combination of the first file and the second file.