Patents by Inventor Abhishek Kumar Dikshit
Abhishek Kumar Dikshit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11340985Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.Type: GrantFiled: August 31, 2020Date of Patent: May 24, 2022Assignee: Fungible, Inc.Inventors: Rajan Goyal, Abhishek Kumar Dikshit
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Patent number: 11010167Abstract: An example integrated circuit includes a memory including a non-deterministic finite automata (NFA) buffer configured to store a plurality of instructions defining an ordered sequence of instructions of at least a portion of an NFA graph, the portion of the NFA graph comprising a plurality of nodes arranged along a plurality of paths. The NFA engine determines a current symbol and one or more subsequent symbols of a payload segment that satisfy a match condition specified by a subset of instructions of the plurality of instructions for a path of the plurality of paths and in response to determining the current symbol and the one or more subsequent symbols of the payload segment that satisfy the match condition, outputs an indication that the payload data has resulted in a match.Type: GrantFiled: May 18, 2020Date of Patent: May 18, 2021Assignee: Fungible, Inc.Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Kumar Dikshit, Yi-Hua Edward Yang, Sandipkumar J. Ladhani
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Patent number: 10990478Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.Type: GrantFiled: February 1, 2019Date of Patent: April 27, 2021Assignee: Fungible, Inc.Inventors: Rajan Goyal, Abhishek Kumar Dikshit, Chris Chinchia Kuo
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Patent number: 10931958Abstract: A device includes a memory configured to store image data and an image coding unit. The image coding unit is configured to determine an indication of a last-non-zero (LNZ) syntax element for a block of image data and determine contexts for coding a coefficient map value for each coefficient of a plurality of coefficients of the block using the LNZ syntax element. The image coding unit is further configured to context-based code the coefficient map value for each of the plurality of coefficients in parallel using the respective contexts.Type: GrantFiled: November 2, 2018Date of Patent: February 23, 2021Assignee: Fungible, Inc.Inventor: Abhishek Kumar Dikshit
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Publication number: 20200401483Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.Type: ApplicationFiled: August 31, 2020Publication date: December 24, 2020Inventors: Rajan Goyal, Abhishek Kumar Dikshit
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Patent number: 10848775Abstract: A device includes a memory configured to store image data and an image coding unit implemented in circuitry. The image coding unit is configured to store a first portion of a set of context information in memory of the image coding unit as an array representing a direct access table and store a second portion of the set of context information in a hash table. The image coding unit is further configured to determine whether a context value for context-based coding of a value of an instance of a syntax element for a block of image data is stored in the array or in the hash table, retrieve the context value from either the array or the hash table according to the determination, and context-based code the value of the instance of the syntax element using the context value.Type: GrantFiled: November 2, 2018Date of Patent: November 24, 2020Assignee: Fungible, Inc.Inventors: Abhishek Kumar Dikshit, Rajan Goyal
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Patent number: 10827192Abstract: A device includes a memory configured to store image data and an image coding unit. The image coding unit is configured to decode a first set of one or more bits of a first value of a first instance of a first syntax element of a block of image data, determine that the first set of one or more bits have values indicating that one or more values of respective instances of one or more other syntax elements of the block of image data are to be decoded. In response to the determination, the image coding unit is configured to decode one or more bits of the one or more values of the respective instances of the one or more other syntax elements of the block prior to decoding a second set of one or more bits of the first value of the first instance of the first syntax element.Type: GrantFiled: November 2, 2018Date of Patent: November 3, 2020Assignee: Fungible, Inc.Inventors: Abhishek Kumar Dikshit, Rajan Goyal, Jorge Cruz-Rios
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Patent number: 10827191Abstract: A device includes a memory configured to store image data and an image coding unit implemented in circuitry. The image coding unit is configured to code a first value of a first instance of a first syntax element of a first block of image data and determine a first context for coding a second value of a second instance of the first syntax element of a second block of the image data. The image coding unit is configured to context-based code the second value of the second instance of the first syntax element of the second block of the image data after coding the first value of the first instance of the first syntax element using the first context and code a third value of a first instance of a second syntax element of the first block in parallel with coding the second value or after coding the second value.Type: GrantFiled: November 2, 2018Date of Patent: November 3, 2020Assignee: Fungible, Inc.Inventors: Abhishek Kumar Dikshit, Jorge Cruz-Rios, Rajan Goyal, Satyanarayana Lakshmipathi Billa
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Publication number: 20200278866Abstract: An example integrated circuit includes a memory including a non-deterministic finite automata (NFA) buffer configured to store a plurality of instructions defining an ordered sequence of instructions of at least a portion of an NFA graph, the portion of the NFA graph comprising a plurality of nodes arranged along a plurality of paths. The NFA engine determines a current symbol and one or more subsequent symbols of a payload segment that satisfy a match condition specified by a subset of instructions of the plurality of instructions for a path of the plurality of paths and in response to determining the current symbol and the one or more subsequent symbols of the payload segment that satisfy the match condition, outputs an indication that the payload data has resulted in a match.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Kumar Dikshit, Yi-Hua Edward Yang, Sandipkumar J. Ladhani
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Patent number: 10761931Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.Type: GrantFiled: October 24, 2018Date of Patent: September 1, 2020Assignee: Fungible, Inc.Inventors: Rajan Goyal, Abhishek Kumar Dikshit
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Publication number: 20200250032Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.Type: ApplicationFiled: February 1, 2019Publication date: August 6, 2020Inventors: Rajan Goyal, Abhishek Kumar Dikshit, Chris Chinchia Kuo
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Patent number: 10656949Abstract: An example processing device includes a memory including a non-deterministic finite automata (NFA) buffer configured to store a plurality of instructions defining an ordered sequence of instructions of at least a portion of an NFA graph, the portion of the NFA graph comprising a plurality of nodes arranged along a plurality of paths. The NFA engine determines a current symbol and one or more subsequent symbols of a payload segment that satisfy a match condition specified by a subset of instructions of the plurality of instructions for a path of the plurality of paths and in response to determining the current symbol and the one or more subsequent symbols of the payload segment that satisfy the match condition, outputs an indication that the payload data has resulted in a match.Type: GrantFiled: July 13, 2018Date of Patent: May 19, 2020Assignee: Fungible, Inc.Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Kumar Dikshit, Yi-Hua Edward Yang, Sandipkumar J. Ladhani
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Publication number: 20200145680Abstract: A device includes a memory configured to store image data and an image coding unit implemented in circuitry. The image coding unit is configured to code a first value of a first instance of a first syntax element of a first block of image data and determine a first context for coding a second value of a second instance of the first syntax element of a second block of the image data. The image coding unit is configured to context-based code the second value of the second instance of the first syntax element of the second block of the image data after coding the first value of the first instance of the first syntax element using the first context and code a third value of a first instance of a second syntax element of the first block in parallel with coding the second value or after coding the second value.Type: ApplicationFiled: November 2, 2018Publication date: May 7, 2020Inventors: Abhishek Kumar Dikshit, Jorge Cruz-Rios, Rajan Goyal, Satyanarayana Lakshmipathi Billa
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Publication number: 20200145682Abstract: A device includes a memory configured to store image data and an image coding unit. The image coding unit is configured to decode a first set of one or more bits of a first value of a first instance of a first syntax element of a block of image data, determine that the first set of one or more bits have values indicating that one or more values of respective instances of one or more other syntax elements of the block of image data are to be decoded. In response to the determination, the image coding unit is configured to decode one or more bits of the one or more values of the respective instances of the one or more other syntax elements of the block prior to decoding a second set of one or more bits of the first value of the first instance of the first syntax element.Type: ApplicationFiled: November 2, 2018Publication date: May 7, 2020Inventors: Abhishek Kumar Dikshit, Rajan Goyal, Jorge Cruz-Rios
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Publication number: 20200145683Abstract: A device includes a memory configured to store image data and an image coding unit. The image coding unit is configured to determine an indication of a last-non-zero (LNZ) syntax element for a block of image data and determine contexts for coding a coefficient map value for each coefficient of a plurality of coefficients of the block using the LNZ syntax element. The image coding unit is further configured to context-based code the coefficient map value for each of the plurality of coefficients in parallel using the respective contexts.Type: ApplicationFiled: November 2, 2018Publication date: May 7, 2020Inventor: Abhishek Kumar Dikshit
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Publication number: 20200145681Abstract: A device includes a memory configured to store image data and an image coding unit implemented in circuitry. The image coding unit is configured to store a first portion of a set of context information in memory of the image coding unit as an array representing a direct access table and store a second portion of the set of context information in a hash table. The image coding unit is further configured to determine whether a context value for context-based coding of a value of an instance of a syntax element for a block of image data is stored in the array or in the hash table, retrieve the context value from either the array or the hash table according to the determination, and context-based code the value of the instance of the syntax element using the context value.Type: ApplicationFiled: November 2, 2018Publication date: May 7, 2020Inventors: Abhishek Kumar Dikshit, Rajan Goyal
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Publication number: 20200133771Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.Type: ApplicationFiled: October 24, 2018Publication date: April 30, 2020Inventors: Rajan Goyal, Abhishek Kumar Dikshit
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Patent number: 10635419Abstract: A compiler/loader unit for a RegEx accelerator is described that receives a first set of regular expression rules for implementing the RegEx accelerator, generates, based on the first set of regular expression rules, an initial deterministic finite automata (DFA) graph, and generates, an initial memory map for allocating the initial DFA graph to a memory of the RegEx accelerator. The compiler/loader unit receives receive, a second set of one or more new or modified regular expression rules for implementing the RegEx accelerator and in response performs incremental compilation of the second set of regular expressions. The compiler/loader unit generates, based on the second set of one or more regular expression rules, a supplemental DFA graph and reconciles the initial DFA graph with the supplemental DFA graph to generate an updated memory map for allocating the initial DFA graph and the supplemental DFA graph to the memory of the RegEx accelerator.Type: GrantFiled: July 13, 2018Date of Patent: April 28, 2020Assignee: Fungible, Inc.Inventors: Yi-Hua Edward Yang, Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Kumar Dikshit
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Publication number: 20200019391Abstract: A compiler/loader unit for a RegEx accelerator is described that receives a first set of regular expression rules for implementing the RegEx accelerator, generates, based on the first set of regular expression rules, an initial deterministic finite automata (DFA) graph, and generates, an initial memory map for allocating the initial DFA graph to a memory of the RegEx accelerator. The compiler/loader unit receives receive, a second set of one or more new or modified regular expression rules for implementing the RegEx accelerator and in response performs incremental compilation of the second set of regular expressions. The compiler/loader unit generates, based on the second set of one or more regular expression rules, a supplemental DFA graph and reconciles the initial DFA graph with the supplemental DFA graph to generate an updated memory map for allocating the initial DFA graph and the supplemental DFA graph to the memory of the RegEx accelerator.Type: ApplicationFiled: July 13, 2018Publication date: January 16, 2020Inventors: Yi-Hua Edward Yang, Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Kumar Dikshit
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Publication number: 20200019404Abstract: An example processing device includes a memory including a non-deterministic finite automata (NFA) buffer configured to store a plurality of instructions defining an ordered sequence of instructions of at least a portion of an NFA graph, the portion of the NFA graph comprising a plurality of nodes arranged along a plurality of paths. The NFA engine determines a current symbol and one or more subsequent symbols of a payload segment that satisfy a match condition specified by a subset of instructions of the plurality of instructions for a path of the plurality of paths and in response to determining the current symbol and the one or more subsequent symbols of the payload segment that satisfy the match condition, outputs an indication that the payload data has resulted in a match.Type: ApplicationFiled: July 13, 2018Publication date: January 16, 2020Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Kumar Dikshit, Yi-Hua Edward Yang, Sandipkumar J. Ladhani