Patents by Inventor Abhishek Kumar Tiwari

Abhishek Kumar Tiwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125956
    Abstract: Enforcement of a communication policy at a communication intermediary configured to communicate between a first communicating entity and a second communicating entity is provided. The communication intermediary includes packet routers. The enforcement includes identifying, by the packet routers of the communication intermediary, a secure plaintext label in each network packet of labeled network traffic received at the packet routers, evaluating whether the labeled network traffic satisfies an enforcement condition of the communication policy based on the secure plaintext label, instructing a network controller to operate on the labeled network traffic according to the communication policy, based on the operation of evaluating. Each network packet includes encrypted content configured to be inaccessible by the packet routers. The secure plaintext label is accessible by the packet routers and includes a data encoding of a portion of the encrypted content.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Inventors: John Wan Yeung SUN, Ashok NANDOORI, Adithya GUNDMI GUNDMI RAMESH, Abhishek Kumar TIWARI
  • Publication number: 20200089801
    Abstract: Methods and devices for data migration may include initially processing requests from a plurality of geographic regions for a cloud service using a global back-end service with a global storage account storing data. The methods and devices may include establishing a region back-end service with a region storage account in at least one geographic region of the plurality of geographic regions to support the cloud service for users in the at least one geographic region, wherein the region back-end service includes a region RTable. The methods and devices may include receiving, by the region back-end service, user requests for the cloud service from one or more users in the at least one geographic region and accessing, via the region RTable, one or more rows of data associated with the at least one geographic region from the global storage account in response to the user requests.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Inventors: Parveen Kumar Patel, Kamel Sbaia, Mohit Garg, Abhishek Agarwal, Bikash Kumar Agrawala, Abhishek Kumar Tiwari
  • Patent number: 8448030
    Abstract: The invention discloses a method and a system for optimizing address generation for simultaneously running proximity-based Built-In-Self-Test (BIST) algorithms. The method also describes simultaneously testing proximity-based faults for different memories having column multiplexers of different sizes using the BIST algorithms. The system described above may be embodied in the form of a Built-In-Self-Test (BIST) controller. Further, the method includes selecting a memory having the largest size of column multiplexer (CMmax). After selecting the memory, size of an address-width register is extended to form an extended address-width register. Thereafter, an extended width address is generated using the extended address-width register and the extended width address is used to generate addresses for the memories. After generating the addresses, read and write operations are performed on the memories based on pre-defined rules, wherein the read and write operations provide testing of the memories.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: May 21, 2013
    Assignee: Interra Systems Inc.
    Inventors: Abhishek Kumar Tiwary, Anubhav Singh, Anuj Verma, Arnab Bhattacharya
  • Publication number: 20120054564
    Abstract: A method and a system for testing memory blocks using a built-in-self-test (BIST) block using a regeneration mechanism. The method includes generation of a test pattern by executing a pre-defined algorithm to test a memory address of a memory block. The test pattern is stored at the memory address, and then the stored data is read from the memory address. The read data is send to a comparator for comparison with a background data. The background data corresponds to the test pattern and is regenerated by a regeneration block corresponding to clock cycles taken for storing the test pattern in the memory address. The stored data is read from the memory address. The comparator generates a validity signal based on the comparison of the background data with the read data.
    Type: Application
    Filed: August 27, 2010
    Publication date: March 1, 2012
    Inventors: Abhishek Kumar Tiwary, Anubhav Singh, Anuj Verma, Arnab Bhattacharya
  • Patent number: 8111929
    Abstract: A method and system for detecting and quantifying blockiness in a video file is disclosed. The video file is a file that has been decompressed by using standard DCT algorithms. The method includes segmenting each frame of the video file into multiple blocks. The method also involves comparing the intensity gradients of each block with one or more threshold values. The one or more threshold values represent predefined intensity variation characteristics. Further, the method includes determining the intensity variation parameters of each block, based on the comparison. Thereafter, a blockiness index is calculated for each block, after which a blockiness value is calculated for each frame. Finally, a blockiness level is assigned to each frame, based on its blockiness value. The blockiness level is a comparative measure of the blockiness of a frame that represents the blockiness content in the frame.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: February 7, 2012
    Assignee: Interra Systems Inc.
    Inventors: Praveen Kumar Tiwari, Abhishek Kumar Tiwary, Anuj Verma, Manik Gupta, Prabhanjana Kumar Nallani
  • Publication number: 20110209012
    Abstract: The invention discloses a method and a system for optimizing address generation for simultaneously running proximity-based Built-In-Self-Test (BIST) algorithms. The method also describes simultaneously testing proximity-based faults for different memories having column multiplexers of different sizes using the BIST algorithms. The system described above may be embodied in the form of a Built-In-Self-Test (BIST) controller. Further, the method includes selecting a memory having the largest size of column multiplexer (CMmax). After selecting the memory, size of an address-width register is extended to form an extended address-width register. Thereafter, an extended width address is generated using the extended address-width register and the extended width address is used to generate addresses for the memories. After generating the addresses, read and write operations are performed on the memories based on pre-defined rules, wherein the read and write operations provide testing of the memories.
    Type: Application
    Filed: December 24, 2010
    Publication date: August 25, 2011
    Inventors: Abhishek Kumar Tiwary, Anubhav Singh, Anuj Verma, Arnab Bhattacharya
  • Publication number: 20090220152
    Abstract: A method and system for detecting and quantifying blockiness in a video file is disclosed. The video file is a file that has been decompressed by using standard DCT algorithms. The method includes segmenting each frame of the video file into multiple blocks. The method also involves comparing the intensity gradients of each block with one or more threshold values. The one or more threshold values represent predefined intensity variation characteristics. Further, the method includes determining the intensity variation parameters of each block, based on the comparison. Thereafter, a blockiness index is calculated for each block, after which a blockiness value is calculated for each frame. Finally, a blockiness level is assigned to each frame, based on its blockiness value. The blockiness level is a comparative measure of the blockiness of a frame that represents the blockiness content in the frame.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventors: Praveen Kumar Tiwari, Abhishek Kumar Tiwary, Anuj Verma, Manik Gupta, Prabhanjana Kumar Nallani