Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for variable rate tessellation. A graphics processor may receive data for geometry processing of a plurality of patches in a draw call. The graphics processor may reduce a tessellation factor of each of the plurality of patches based on a property of each of the plurality of patches. The reduced tessellation factor may correspond to a TRF. The property may correspond to a shading rate or a number of visible pixels. The graphics processor may apply the TRF for each of the plurality of patches. The graphics processor may render each of the plurality of patches based on the applied TRF for each of the plurality of patches.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for variable rate tessellation. A graphics processor may receive data for geometry processing of a plurality of patches in a draw call. The graphics processor may reduce a tessellation factor of each of the plurality of patches based on a property of each of the plurality of patches. The reduced tessellation factor may correspond to a TRF. The property may correspond to a shading rate or a number of visible pixels. The graphics processor may apply the TRF for each of the plurality of patches. The graphics processor may render each of the plurality of patches based on the applied TRF for each of the plurality of patches.

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.

Abstract: A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of Vglitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage Vtrip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage Vbias, wherein Vbias is chosen such that either both conditions (Vbias<Vtrip) and (Vbias+Vglitch>Vtrip) or both conditions (Vbias>Vtrip) and (Vbias?Vglitch<Vtrip) are always true.

Abstract: A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of Vglitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage Vtrip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage Vbias, wherein Vbias is chosen such that either both conditions (Vbias<Vtrip) and (Vbias+Vglitch>Vtrip) or both conditions (Vbias>Vtrip) and (Vbias?Vglitch<Vtrip) are always true.

Abstract: According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.

Abstract: A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first level decode lines and a second level decoder that decodes between the first level decode lines and second level decode lines. The second level decoder includes first transistors coupled between the first level decode lines and read output lines and second transistors coupled between the first level decode lines and write input lines. The first transistors have a first voltage rating and are driven by decode control signals referenced to a low supply voltage compatible with the first voltage rating. The second transistors have a second voltage rating, higher than the first voltage rating, and are driven by decode control signals referenced to a high supply voltage (in excess of the low supply voltage) compatible with the second voltage rating.

Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.

Abstract: According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.

Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract: A fail-safe level shifter switching with high speed and operational for a wide range of voltage supply includes a cascode module, and one or more speed enhancer modules. The cascode module receives one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.

Abstract: The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level.

Abstract: The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level.

Abstract: The present invention discloses a fail-safe level shifter switching with high speed and operational for a wide range of voltage supply. The level shifter includes a cascode module, and one or more speed enhancer modules. The cascode module is receiving one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.

Abstract: An improved binary decoder incorporating a selection circuit that activates a selected output corresponding to a input binary value, and a deselecting circuit coupled to each output that deactivates all other outputs when the selected output is activated. The deselecting circuit arrangement has a single input connected to the selected output and a plurality of outputs each of which is connected to one of the remaining outputs and forces them to the inactive state whenever the selected output is activated.

Abstract: An improved binary decoder incorporating a selection circuit that activates a selected output corresponding to a input binary value, and a deselecting circuit coupled to each output that deactivates all other outputs when the selected output is activated. The deselecting circuit arrangement has a single input connected to the selected output and a plurality of outputs each of which is connected to one of the remaining outputs and forces them to the inactive state whenever the selected output is activated.