Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.

Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.

Abstract: A description of a machine learning (ML) model is received, with the ML model including multiple features such as an unlikely combination feature, which corresponds to a first attribute to be located in an invoice and a second attribute to be located the invoice concurrently with the first attribute. Training data is received, including (i) invoice data with multiple invoices, each including the first attribute and the second attribute, and respective values of the first attribute and the second attribute, and (ii) validity data including indications of which of the invoices are valid and which of the invoices are invalid. The ML model is trained using the training data using the ML model. The training includes applying the values of the attributes to the unlikely combination feature. The ML model is applied to an invoice to be validated to determine a probability that the invoice is invalid.

Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.

Abstract: A description of a machine learning (ML) model is received, with the ML model including multiple features such as an unlikely combination feature, which corresponds to a first attribute to be located in an invoice and a second attribute to be located the invoice concurrently with the first attribute. Training data is received, including (i) invoice data with multiple invoices, each including the first attribute and the second attribute, and respective values of the first attribute and the second attribute, and (ii) validity data including indications of which of the invoices are valid and which of the invoices are invalid. The ML model is trained using the training data using the ML model. The training includes applying the values of the attributes to the unlikely combination feature. The ML model is applied to an invoice to be validated to determine a probability that the invoice is invalid.

Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.