Patents by Inventor Abhishek PATYAL

Abhishek PATYAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for layout generation with constrained hypergraph partitioning
    Patent number: 10509883
    Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang, Hung-Ming Chen, Abhishek Patyal
  • METHOD FOR LAYOUT GENERATION WITH CONSTRAINED HYPERGRAPH PARTITIONING
    Publication number: 20180150585
    Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 31, 2018
    Inventors: Tsun-Yu YANG, Wei-Yi HU, Jui-Feng KUAN, Hsien-Hsin Sean LEE, Po-Cheng PAN, Hung-Wen HUANG, Hung-Ming CHEN, Abhishek PATYAL