Abstract: An apparatus is provided having processing circuitry for executing multiple items of supervised software under the control of a supervising element, and a set associative address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system comprising multiple pages. The address translation data is obtained by a multi-stage address translation process comprising a first stage translation process managed by an item of supervised software and a second stage translation process managed by the supervising element.

Abstract: An apparatus and method are provided for making efficient use of address translation cache resources. The apparatus has an address translation cache having a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each item of address translation data has a page size indication for a page within the memory system that is associated with that address translation data. Allocation circuitry performs an allocation process to determine the address translation data to be stored in each entry. Further, mode control circuitry is used to switch a mode of operation of the apparatus between a non-skewed mode and at least one skewed mode, dependent on a page size analysis operation.

Abstract: An apparatus and method are provided for accessing an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. The virtual address is generated from a plurality of source values. Allocation circuitry is responsive to received address translation data, to allocate an entry within the address translation cache to store the received address translation data. A hash value indication is associated with the allocated entry, where the hash value indication is computed from the plurality of source values used to generate a virtual address associated with the received address translation data.

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing a plurality of instructions. Storage circuitry stores a plurality of entries, each entry relating to an instruction in the plurality of instructions and including a dependency field. The dependency field stores a data dependency of that instruction on a previous instruction in the plurality of instructions. Scheduling circuitry schedules the execution of the plurality of instructions in an order that depends on each data dependency. When the previous instruction is a single-cycle instruction, the dependency field includes a reference to one of the entries that relates to the previous instruction, otherwise, the data dependency field includes an indication of an output destination of the previous instruction.

Abstract: An apparatus and method are provided for determining address translation data to be stored within an address translation cache. The apparatus comprises an address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. Via an interface of the apparatus, access requests are received from a request source, where each access request identifies a virtual address. Prefetch circuitry is responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages.

Abstract: An apparatus and method are provided for accessing an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. The virtual address is generated from a plurality of source values. Allocation circuitry is responsive to received address translation data, to allocate an entry within the address translation cache to store the received address translation data. A hash value indication is associated with the allocated entry, where the hash value indication is computed from the plurality of source values used to generate a virtual address associated with the received address translation data.

Abstract: An apparatus is provided having processing circuitry for executing multiple items of supervised software under the control of a supervising element, and a set associative address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system comprising multiple pages. The address translation data is obtained by a multi-stage address translation process comprising a first stage translation process managed by an item of supervised software and a second stage translation process managed by the supervising element.

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. The address translation cache is used to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk. The plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address.

Abstract: An apparatus and method are provided for determining address translation data to be stored within an address translation cache. The apparatus comprises an address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. Via an interface of the apparatus, access requests are received from a request source, where each access request identifies a virtual address. Prefetch circuitry is responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages.

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. When performing the allocation process for a selected entry, the control circuitry is arranged to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address. The control circuitry then determines whether predetermined criteria are met by the plurality of descriptors, the predetermined criteria comprising page alignment criteria and attribute match criteria.

Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.

Abstract: An apparatus and method are provided for making efficient use of address translation cache resources. The apparatus has an address translation cache having a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each item of address translation data has a page size indication for a page within the memory system that is associated with that address translation data. Allocation circuitry performs an allocation process to determine the address translation data to be stored in each entry. Further, mode control circuitry is used to switch a mode of operation of the apparatus between a non-skewed mode and at least one skewed mode, dependent on a page size analysis operation.

Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. The address translation cache is used to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk. The plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address.

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. When performing the allocation process for a selected entry, the control circuitry is arranged to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address. The control circuitry then determines whether predetermined criteria are met by the plurality of descriptors, the predetermined criteria comprising page alignment criteria and attribute match criteria.