Abstract: A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and nanocrystals within the depletion region, with each nanocrystal comprising a semiconductor material and carbon. The memory device may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

Abstract: A method for making a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions, and trap source atoms within the stacked groups of layers. Each memory call may also include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

Abstract: A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Trap source atoms may also be within the stacked groups of layers. Each memory cell may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

Abstract: A method for making a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and nanocrystals within the depletion region, with each nanocrystal comprising a semiconductor material and carbon. The memory device may further include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.