Abstract: An apparatus comprises a first tile comprising a first instance of a plurality of global endpoints and a first instance of a plurality of local networks comprising a plurality of local endpoints; and an interconnect network of the first tile to couple to an interconnect network of a second tile, the second tile comprising a second instance of the plurality of global endpoints and a second instance of the plurality of local networks comprising the plurality of local endpoints; wherein the interconnect network utilizes an address space comprising unique identifiers for the plurality of global endpoints of the first and second tiles; and non-unique identifiers for the plurality of local endpoints of the first and second tiles, wherein non-unique identifiers are reused in multiple local networks of the plurality of local networks of the first and second tiles.

Abstract: A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a fabric comprising a handler circuitry to decode a request from a compute engine, the handler circuitry to route the request based on an opcode included in the request, the handler configured to decode the opcode from a set of opcodes for use in requests by the compute engine, wherein the set of opcodes include opcodes corresponding to a first write request type and a first read request type, wherein requests of the first write request type and the first read request type are routed to either the host memory or the graphics memory; and a second write request type and a second read request type, wherein requests of the second write request type and the second request type are to be routed to the sideband network.