Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

Abstract: A method includes processing event data to detect a status of a network function. The event data is processed based on two or more conditions defined by a correlation policy. The correlation policy includes a non-deterministic finite automata tree (NFAT) structure correlation policy having a policy type. The method also includes determining a first value of a first condition of the two or more conditions. The method further includes determining a second value of a second condition of the two or more conditions. The method additionally includes determining the policy type of the NFAT structure correlation policy. The method also includes determining whether the first value is greater than a first preset value indicative of whether the first condition is satisfied. The method further includes determining whether the second value is greater than a second preset value indicative of whether the second condition is satisfied.

Abstract: Described herein are stacked memory devices that include some peripheral devices for controlling the memory in a separate layer from one or more memory arrays. The layers of the memory device are connected together using vias, which transfer power and data between the layers. In some examples, a portion of the peripheral devices are included in a memory layer, and another portion are included in a peripheral device layer. Multiple layers of memory arrays and/or peripheral devices may be included, e.g., one peripheral device layer may control multiple layers of memory arrays, or different layers of memory arrays may have dedicated peripheral device layers. Different types of memory arrays, such as DRAM or SRAM, may be included.

Abstract: Embodiments include a resistive random access memory (RRAM) storage cell, having a resistive switching material layer and a semiconductor layer between two electrodes, where the semiconductor layer serves as an OEL. In addition, the RRAM storage cell may be coupled with a transistor to form a RRAM memory cell. The RRAM memory cell may include a semiconductor layer as a channel for the transistor, and also shared with the storage cell as an OEL for the storage cell. A shared electrode may serve as a source electrode of the transistor and an electrode of the storage cell. In some embodiments, a dielectric layer may be shared between the transistor and the storage cell, where the dielectric layer is a resistive switching material layer of the storage cell.

Abstract: A network operating system (NOS) receives a bundle file transmitted from a vendor terminal of a vendor providing a network service, the bundle file including first data defining a functional unit group that achieves the network service and second data defining a monitoring policy for the network service. The NOS constructs the functional unit group based on the first data of the bundle file when the network service is purchased by a purchaser. The NOS executes a monitoring process on the functional unit group based on information on the functional unit group to be constructed and the second data of the bundle file.

Abstract: A network operating system (NOS) acquires, for a plurality of network functions that achieve a network slice constructed on a mobile wireless communication network, information on an operation of each network function which is measured by one or more apparatus configured to provide at least a part of the plurality of network functions. The NOS derives an evaluation index value of each of the plurality of network functions based on the information on the operation of each of the plurality of network functions, and derives an evaluation index value of the network slice based on the evaluation index values of the plurality of network functions.

Abstract: Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also deposited or layer transferred onto the PIC assembly.

Abstract: Described herein are hybrid IC assemblies that include multiple stacked layers of electronic and/or photonic circuit elements. For example, a first layer of the IC assembly includes a waveguide formed of a substantially monocrystalline material, and a second layer of the IC assembly includes at least one electronic circuit element. A bonding material between a front face of the first layer and a back face of the second layer attaches the first layer to the second layer. The bonding material has a lower crystallinity than the waveguide.

Abstract: A device is disclosed. The device includes a plurality of capacitors, a transistor connected to each of the plurality of capacitors, and a first dielectric layer and a second dielectric layer on respective adjacent sides of adjacent capacitors of the plurality of capacitors. The first dielectric layer and the second dielectric layer include a top portion and a bottom portion, the top portion of the first dielectric layer and the top portion of the second dielectric layer extend from respective directions and meet at a top portion of a space between the adjacent capacitors, the bottom portion of the first dielectric layer and the bottom portion of the second dielectric layer extend from respective directions and meet at a bottom portion of a space between the adjacent capacitors.

Abstract: A method and an apparatus for managing a service request in a blockchain network are provided. The method includes receiving, by a first device, a service request, identifying an intent from the service request, selecting one or more atomic contracts, each of which is related to the intent, wherein the atomic contracts are associated with a second device on the blockchain network and are verified in the blockchain network, generating a new contract including the atomic contracts, and broadcasting the new contract over the blockchain network.

Abstract: A DRAM integrated circuit device is described in which at least some of the peripheral circuits associated with the memory arrays are provided on a first substrate. The memory arrays are provided on a second substrate stacked on the first substrate, thus forming a DRAM integrated circuit device on a stacked-substrate assembly. Vias that electrically connect the memory arrays on the second substrate to the peripheral circuits on the first substrate are fabricated using high aspect ratio via fabrication techniques.

Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit (IC) assemblies with stacked compute logic and memory dies, and associated systems and methods, are disclosed. One example IC assembly includes a compute logic die and a stack of memory dies provided above and coupled to the compute logic die, where one or more of the memory dies closest to the compute logic die include memory cells with transistors that are thin-film transistors (TFTs), while one or more of the memory dies further away from the compute logic die include memory cells with non-TFT transistors. Another example IC assembly includes a similar stack of compute logic die and memory dies where one or more of the memory dies closest to the compute logic die include static random-access memory (SRAM) cells, while one or more of the memory dies further away from the compute logic die include memory cells of other memory types.

Abstract: A method includes causing a message bus to send event data received from an observability framework to one or more data enrichers based on a multi-layered correlation policy. The multi-layered correlation policy is communicated to the message bus by a policy definition manager. The policy definition manager is connected to a database that includes a plurality of rules associated with monitoring and modifying one or more network functions associated with a communication network. The policy definition manager is configured to generate the multi-layered correlation policy based on one or more of the rules. The method also includes causing a policy action manager to trigger an operation to be performed by a lifecycle manager. The operation is defined by the multi-layered correlation policy as an action caused to occur based on a determination of whether the event data satisfies one or more conditions defined by the multi-layered correlation policy.

Abstract: A method includes processing a user input for generating a non-deterministic finite automata tree (NFAT) correlation policy. The user input indicates one or more of a static condition or a dynamic condition for inclusion in the NFAT correlation policy. The static condition includes a comparison between a defined entity and a first fixed parameter. The dynamic condition includes a comparison between the defined entity and a variable parameter. An applicable NFAT element is generated that includes at least one of the NFAT correlation policy generated based on a determination that the user input indicates the static condition or a NFAT template generated based on a determination that the user input indicates the dynamic condition. Event data received from a network device is processed to detect a status of a network entity associated with a communication network based on the applicable NFAT element.

Abstract: A technique implements a dataflow graph, taking a number of streams of data inputs and transforms these inputs into a number of streams of outputs. The dataflow graph can perform pattern matching. The technique implements reactions via the composition of pattern matching across joined streams of input data. A completeness of matching an input sequence to a particular input pattern can be characterized as having at least three different degrees, such as cold (not yet matched), warm (e.g., minimally matched), and hot (e.g., maximally matched). The input pattern to be matched can have a variable length, including zero length or unlimited or arbitrarily large length. Data flows can be on a push basis or pull basis, or a combination, and may change depending on the state.

Abstract: Image-based key points detection using a convolutional neural network (CNN) may be impacted if the key points are occluded in the image. Images obtained from additional imaging modalities such as depth and/or thermal images may be used in conjunction with RGB images to reduce or minimize the impact of the occlusion. The additional images may be used to determine adjustment values that are then applied to the weights of the CNN so that the convolution operations may be performed in a modality aware manner to increase the robustness, accuracy, and efficiency of key point detection.

Abstract: A method includes creating a package of an application, registering the package with an orchestrator, triggering instantiation of the application in the orchestrator, generating initial configuration files for the instantiation of the application, changing an application state of the application to a planned state, changing the application state to a Keycloak state in response to obtaining client identification of the Keycloak information for the application, changing the application state to an instantiated state in response to deploying the application on the set of target servers, changing the application state to a configured state in response applying daily configuration files to perform daily configuration of the application in the set of target servers, and changing the application state to a monitored state in response to monitoring the application in the set of target servers by an observability framework tool.

Abstract: Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

Abstract: Memory cells with non-planar memory materials that include FE or AFE materials are described. An example memory cell includes a transistor provided over a support structure, where a memory material is integrated with a transistor gate. The channel material and the memory material are non-planar in that each includes a horizontal portion substantially parallel to the support structure, and a first and a second sidewall portions, each of which is substantially perpendicular to the support structure, where the horizontal portion of the memory material is between the horizontal portion of the channel material and a gate electrode material of the transistor gate, the first sidewall of the memory material is between the first sidewall of the channel material and the gate electrode material, and the second sidewall of the memory material is between the second sidewall of the channel material and the gate electrode material.