Patents by Inventor Abhishek Sinha

Abhishek Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240375118
    Abstract: A pyramid lining insert/element for mill drum of a grinding mill, comprising of a structural and positional formation of pyramid inserts configured with a front lifter part that extends a first side of the liner member with a defined height and a real lifter part that extends to the rear side conforming shape of pyramid of the said liner member; wherein both the front and rear lifter part having an height; and wherein the said front and rear lifter part are adjacent to each other along the side of the said pyramid shaped lining member and have a front and rear support plate beneath the said front and rear lifter part in order to support the lifter plate and also to provide a robust and solid lining member.
    Type: Application
    Filed: November 26, 2022
    Publication date: November 14, 2024
    Inventors: Abhishek SINHA, Juan Eduardo Bustamante HERNANDEZ
  • Patent number: 12141578
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20240354043
    Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
    Type: Application
    Filed: April 29, 2024
    Publication date: October 24, 2024
    Inventors: Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
  • Patent number: 12124310
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: October 22, 2024
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Publication number: 20240320184
    Abstract: Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.
    Type: Application
    Filed: March 28, 2024
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Altug Koker, Ben Ashbaugh, Scott Janus, Aravindh Anantaraman, Abhishek R. Appu, Niranjan Cooray, Varghese George, Arthur Hunter, Brent E. Insko, Elmoustapha Ould-Ahmed-Vall, Selvakumar Panneer, Vasanth Ranganathan, Joydeep Ray, Kamal Sinha, Lakshminarayanan Striramassarma, Prasoonkumar Surti, Saurabh Tangri
  • Patent number: 12099461
    Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 14, 2020
    Date of Patent: September 24, 2024
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei, Nicolas Galoppo Von Borries, Varghese George, Mike Macpherson, Subramaniam Maiyuran, Joydeep Ray, Lakshminarayanan Striramassarma, Scott Janus, Brent Insko, Vasanth Ranganathan, Kamal Sinha, Arthur Hunter, Prasoonkumar Surti, David Puffer, James Valerio, Ankur N. Shah
  • Patent number: 12061831
    Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
  • Publication number: 20240264657
    Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
    Type: Application
    Filed: March 11, 2024
    Publication date: August 8, 2024
    Inventors: Altug Koker, Abhishek R. Appu, Bhushan M. Borole, Wenyin Fu, Kamal Sinha, Joydeep Ray
  • Publication number: 20240256456
    Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the Li cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.
    Type: Application
    Filed: December 20, 2023
    Publication date: August 1, 2024
    Applicant: Intel Corporation
    Inventors: Vikranth Vemulapalli, Lakshminarayanan Striramassarma, Mike MacPherson, Aravindh Anantaraman, Ben Ashbaugh, Murali Ramadoss, William B. Sadler, Jonathan Pearce, Scott Janus, Brent Insko, Vasanth Ranganathan, Kamal Sinha, Arthur Hunter, Jr., Prasoonkumar Surti, Nicolas Galoppo von Borries, Joydeep Ray, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Altug Koker, Sungye Kim, Subramaniam Maiyuran, Valentin Andrei
  • Publication number: 20240257294
    Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
    Type: Application
    Filed: February 8, 2024
    Publication date: August 1, 2024
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • Patent number: 12039331
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: July 16, 2024
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Patent number: 11972466
    Abstract: A search system provides search results with images of products based on associations of primary products and secondary products from product image sets. The search system analyzes a product image set containing multiple images to determine a primary product and secondary products. Information associating the primary and secondary products are stored in a search index. When the search system receives a query image containing a search product, the search index is queried using the search product to identify search result images based on associations of products in the search index, and the result images are provided as a response to the query image.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 30, 2024
    Assignee: ADOBE INC
    Inventors: Jonas Dahl, Mausoom Sarkar, Hiresh Gupta, Balaji Krishnamurthy, Ayush Chopra, Abhishek Sinha
  • Patent number: 11829880
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for generating trained neural network with increased robustness against adversarial attacks by utilizing a dynamic dropout routine and/or a cyclic learning rate routine. For example, the disclosed systems can determine a dynamic dropout probability distribution associated with neurons of a neural network. The disclosed systems can further drop neurons from a neural network based on the dynamic dropout probability distribution to help neurons learn distinguishable features. In addition, the disclosed systems can utilize a cyclic learning rate routine to force copy weights of a copy neural network away from weights of an original neural network without decreasing prediction accuracy to ensure that the decision boundaries learned are different.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: November 28, 2023
    Assignee: Adobe Inc.
    Inventors: Mayank Singh, Nupur Kumari, Dhruv Khattar, Balaji Krishnamurthy, Abhishek Sinha
  • Patent number: 11734337
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer-readable media for generating tags for an object portrayed in a digital image based on predicted attributes of the object. For example, the disclosed systems can utilize interleaved neural network layers of alternating inception layers and dilated convolution layers to generate a localization feature vector. Based on the localization feature vector, the disclosed systems can generate attribute localization feature embeddings, for example, using some pooling layer such as a global average pooling layer. The disclosed systems can then apply the attribute localization feature embeddings to corresponding attribute group classifiers to generate tags based on predicted attributes. In particular, attribute group classifiers can predict attributes as associated with a query image (e.g., based on a scoring comparison with other potential attributes of an attribute group).
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: August 22, 2023
    Assignee: Adobe Inc.
    Inventors: Ayush Chopra, Mausoom Sarkar, Jonas Dahl, Hiresh Gupta, Balaji Krishnamurthy, Abhishek Sinha
  • Patent number: 11734565
    Abstract: Embodiments disclosed herein describe systems, methods, and products that generate trained neural networks that are robust against adversarial attacks. During a training phase, an illustrative computer may iteratively optimize a loss function that may include a penalty for ill-conditioned weight matrices in addition to a penalty for classification errors. Therefore, after the training phase, the trained neural network may include one or more well-conditioned weight matrices. The one or more well-conditioned weight matrices may minimize the effect of perturbations within an adversarial input thereby increasing the accuracy of classification of the adversarial input. By contrast, conventional training approaches may merely reduce the classification errors using backpropagation, and, as a result, any perturbation in an input is prone to generate a large effect on the output.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: August 22, 2023
    Assignee: Adobe Inc.
    Inventors: Mayank Singh, Abhishek Sinha, Balaji Krishnamurthy
  • Publication number: 20230107574
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for generating trained neural network with increased robustness against adversarial attacks by utilizing a dynamic dropout routine and/or a cyclic learning rate routine. For example, the disclosed systems can determine a dynamic dropout probability distribution associated with neurons of a neural network. The disclosed systems can further drop neurons from a neural network based on the dynamic dropout probability distribution to help neurons learn distinguishable features. In addition, the disclosed systems can utilize a cyclic learning rate routine to force copy weights of a copy neural network away from weights of an original neural network without decreasing prediction accuracy to ensure that the decision boundaries learned are different.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 6, 2023
    Inventors: Mayank Singh, Nupur Kumari, Dhruv Khattar, Balaji Krishnamurthy, Abhishek Sinha
  • Patent number: 11481617
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for generating trained neural network with increased robustness against adversarial attacks by utilizing a dynamic dropout routine and/or a cyclic learning rate routine. For example, the disclosed systems can determine a dynamic dropout probability distribution associated with neurons of a neural network. The disclosed systems can further drop neurons from a neural network based on the dynamic dropout probability distribution to help neurons learn distinguishable features. In addition, the disclosed systems can utilize a cyclic learning rate routine to force copy weights of a copy neural network away from weights of an original neural network without decreasing prediction accuracy to ensure that the decision boundaries learned are different.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 25, 2022
    Assignee: Adobe Inc.
    Inventors: Mayank Singh, Nupur Kumari, Dhruv Khattar, Balaji Krishnamurthy, Abhishek Sinha
  • Patent number: 11468314
    Abstract: Embodiments disclosed herein describe systems, methods, and products that generate trained neural networks that are robust against adversarial attacks. During a training phase, an illustrative computer may iteratively optimize a loss function that may include a penalty for ill-conditioned weight matrices in addition to a penalty for classification errors. Therefore, after the training phase, the trained neural network may include one or more well-conditioned weight matrices. The one or more well-conditioned weight matrices may minimize the effect of perturbations within an adversarial input thereby increasing the accuracy of classification of the adversarial input. By contrast, conventional training approaches may merely reduce the classification errors using backpropagation, and, as a result, any perturbation in an input is prone to generate a large effect on the output.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 11, 2022
    Assignee: Adobe Inc.
    Inventors: Mayank Singh, Abhishek Sinha, Balaji Krishnamurthy
  • Publication number: 20220309093
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer-readable media for generating tags for an object portrayed in a digital image based on predicted attributes of the object. For example, the disclosed systems can utilize interleaved neural network layers of alternating inception layers and dilated convolution layers to generate a localization feature vector. Based on the localization feature vector, the disclosed systems can generate attribute localization feature embeddings, for example, using some pooling layer such as a global average pooling layer. The disclosed systems can then apply the attribute localization feature embeddings to corresponding attribute group classifiers to generate tags based on predicted attributes. In particular, attribute group classifiers can predict attributes as associated with a query image (e.g., based on a scoring comparison with other potential attributes of an attribute group).
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Inventors: Ayush Chopra, Mausoom Sarkar, Jonas Dahl, Hiresh Gupta, Balaji Krishnamurthy, Abhishek Sinha
  • Publication number: 20220292356
    Abstract: Embodiments disclosed herein describe systems, methods, and products that generate trained neural networks that are robust against adversarial attacks. During a training phase, an illustrative computer may iteratively optimize a loss function that may include a penalty for ill-conditioned weight matrices in addition to a penalty for classification errors. Therefore, after the training phase, the trained neural network may include one or more well-conditioned weight matrices. The one or more well-conditioned weight matrices may minimize the effect of perturbations within an adversarial input thereby increasing the accuracy of classification of the adversarial input. By contrast, conventional training approaches may merely reduce the classification errors using backpropagation, and, as a result, any perturbation in an input is prone to generate a large effect on the output.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 15, 2022
    Inventors: Mayank SINGH, Abhishek SINHA, Balaji KRISHNAMURTHY