Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672515
    Abstract: Methods and devices for retrospectively assessing continuous monitoring reference pattern data to determine a risk of a patient glucose level measurement taken in at least one data segment being outside a predetermined range. The methods and devices can include executing an algorithm to compare risk scores derived from reference pattern data in a currently collected data segment with risk scores of previously stored reference pattern data of previously collected data segments for a patient for assessing risk.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 2, 2020
    Assignee: Roche Diabetes Care, Inc.
    Inventors: Abhishek Soni, David L. Duke
  • Publication number: 20200168634
    Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 28, 2020
    Inventors: Abhishek A. SHARMA, Van H. LE, Seung Hoon SUNG, Ravi PILLARISETTY, Marko RADOSAVLJEVIC
  • Publication number: 20200168274
    Abstract: One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 28, 2020
    Inventors: Ravi PILLARISETTY, Abhishek A. SHARMA, Brian S. DOYLE, Elijah V. KARPOV, Prashant MAJHI
  • Publication number: 20200167570
    Abstract: A multi-view interactive digital media representation (MVIDMR) of an object can be generated from live images of an object captured from a camera. Selectable tags can be placed at locations on the object in the MVIDMR. When the selectable tags are selected, media content can be output which shows details of the object at location where the selectable tag is placed. A machine learning algorithm can be used to automatically recognize landmarks on the object in the frames of the MVIDMR and a structure from motion calculation can be used to determine 3-D positions associated with the landmarks. A 3-D skeleton associated with the object can be assembled from the 3-D positions and projected into the frames associated with the MVIDMR. The 3-D skeleton can be used to determine the selectable tag locations in the frames of the MVIDMR of the object.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: Fyusion, Inc.
    Inventors: Chris Beall, Abhishek Kar, Stefan Johannes Josef Holzer, Radu Bogdan Rusu, Pavel Hanchar
  • Publication number: 20200167159
    Abstract: A process for processor testing includes dividing a memory space into first and second portions and generating first and second sets of test instructions for the respective first and second portion. The first and second sets each include a plurality of counter increment/branch instruction pairs where each branch instruction of the first set branches to a backward instruction location and each branch instruction of the second set branches to a forward instruction location.
    Type: Application
    Filed: January 29, 2020
    Publication date: May 28, 2020
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Publication number: 20200165542
    Abstract: The present invention provides a liquid detergent composition comprising anionic surfactants, optionally one or more nonionic surfactants, polyethylene glycol, and water, and wherein the liquid detergent composition has a pH of 7.0 to 7.5, wherein the liquid detergent composition has a viscosity at 25° C. and 20 s?1 in the range of 5 to 100 mPa s?1, and wherein the liquid laundry composition has stable viscosity between a temperature range of 10 and 40° C., and wherein the composition is adapted for application with a hand-held dispensing device used for washing by hand. The liquid detergent composition has a low constant viscosity throughout the temperature range of normal use and produces a stable foamy lather.
    Type: Application
    Filed: May 30, 2018
    Publication date: May 28, 2020
    Inventors: Jonathan Best, Panchanan Bhunia, Robert John Carswell, Richa Sureshchand Goyal, Sujitkumar Suresh Hibare, Alagirisamy Nethaji, Abhishek Rastogi, Savitha Sudhir
  • Publication number: 20200168636
    Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the In topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: September 15, 2017
    Publication date: May 28, 2020
    Inventors: Prashant MAJHI, Brian S. DOYLE, Ravi PILLARISETTY, Abhishek A. SHARMA, Elijah V. KARPOV
  • Publication number: 20200169496
    Abstract: Some embodiments provide a method for implementing a logical network. Based on logical network configuration data, the method identifies a route for a set of network addresses to add to a routing table of the logical router, and also identifies a route type for the identified route. The method determines whether to include the identified route as a route for the logical router to advertise based on the route type of the identified route. The method distributes a routing table comprising the identified route to a computing device that implements the logical router, where the computing device advertises the identified route when the route type is specified for advertisement.
    Type: Application
    Filed: February 14, 2019
    Publication date: May 28, 2020
    Inventors: ABHISHEK GOLIYA, ANKUR DUBEY
  • Publication number: 20200167604
    Abstract: Embodiments for creating compact example subsets for intent classification in a conversational system are provided. A set of content used for training an intent classifier is received from a conversational corpus. Entries within the set of content are separated into a first subset and a second subset, and a cross-validation operation is performed on the first and second subsets to identify a correctly labeled portion and an incorrectly labeled portion of the set of content. A reduced content used for performing a final training of the intent classifier is formed by combining a first number of the entries from the correctly labeled portion and a second number of the entries from the incorrectly labeled portion of the set of content.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek SHAH, Tin Kam HO
  • Publication number: 20200167431
    Abstract: In an automatic context adaptive search and result generation, a server obtains an email corpus of a user for a current time period. The server identifies a set of triggering semantics in the email corpus, and using an ontology, identifies a set of topic-context pairs corresponding to each triggering semantic. The server identifies a set of paths in the ontology activated by the set of topic-context pairs and compares the set of activated paths with paths in each heatmap of a set of heatmaps, where each heatmap corresponds to a document in a set of documents. The server identifies one or more heatmaps of the set of heatmaps including one or more paths matching an activated path of the set of activated paths. The server then outputs a search result including the one or more documents corresponding to the one or more heatmaps.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Inventors: Abhishek MITRA, Suranjana SAMANTA, Geetha ADINARAYAN
  • Patent number: 10664824
    Abstract: Techniques for enhancing the security of a communication device when conducting a transaction using the communication device may include receiving a cryptogram generation key replenishment request that includes transaction log information derived from transaction data stored in a transaction log on a communication device, verifying that the transaction log information in the replenishment request is consistent with the previously received transaction information, and providing a new cryptogram generation key to the communication device in response to verifying the transaction log information in the replenishment request.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: May 26, 2020
    Assignee: Visa International Service Association
    Inventors: Erick Wong, Christian Flurscheim, Oleg Makhotin, Eduardo Lopez, Sanjeev Sharma, Christopher Jones, Abhishek Guglani, Jarkko Oskari Sevanto, Bharatkumar Patel, Tai Lung Burnnet Or, Christian Aabye, Hao Ngo, John F. Sheets
  • Patent number: 10664594
    Abstract: Methods for accelerated code injection detection using operating system controlled memory attributes are performed by systems and apparatuses. The methods optimize search operations for memory segments in system and virtual memories by searching for segment attributes. A set of memory segments is determined wherein each memory segment in the set includes specific attributes. The memory segments in the set are ranked for a threat level based on segment attribute. The threat level is used to determine subsequent actions including providing indications of the memory segments in the set and initiating execution of an anti-malware application. Relevant segment attributes used for the segment search can be dynamically updated in an attribute list. Segment attributes of a segment can be determined by accessing a memory manager of an operating system via an API.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 26, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Abhishek Kumar Singh, Aditya Joshi, Freddie L. Aaron, Peter A. Loveless, Tino Morenz
  • Publication number: 20200160484
    Abstract: Embodiments provide for a graphics processing apparatus including a cache memory and logic coupled to the cache memory to compress color data output from the first cache memory. In one embodiment the cache memory is a render cache. In one embodiment the cache memory is a victim data cache. In one embodiment the first cache memory is a render cache coupled to a victim data cache and logic is configured to compress color data evicted from the render cache and the victim data cache. The compression can include a target compression ratio to which the data is to be compressed.
    Type: Application
    Filed: October 11, 2019
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Prasoonkumar Surti, Hiroshi Akiba
  • Publication number: 20200160271
    Abstract: A computer implemented method includes collecting collaboration information containing data representative of collaborations between at least two individuals, applying time allocation heuristics to the collected collaboration data to extract respective collaborations times for the at least two individuals, storing the extracted collaborations times on a storage device, and accessing the storage device to process queries regarding collaboration between the at least two individuals.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 21, 2020
    Inventors: Chantrelle Nielsen, Nikolay Mitev Trandev, Brett Daniel Mills, Dheepak Ramaswamy, Si Meng, Zoey Jennifer Geary, Mugdha Kolhatkar, Pracheer Agarwal, Shubham Aggarwal, Tapas Bansal, Siddarth Rejendra Kumar, Abhishek Kalai Raghavendra, Jagadeesh Huliyar, Sanjay H. Ramaswamy, Sai Sumana Pagidipalli, Shubham Aggarwal, Sreeram Nivarthi
  • Publication number: 20200159969
    Abstract: Systems, apparatuses, methods, and computer-readable media are provided for device interface management. A device includes a device interface, a virtual machine (VM) includes a device driver, both to facilitate assignment of the device to the VM, access of the device by the VM, or removal of the device from being assigned to the VM. The VM is managed by a hypervisor of a computing platform coupled to the device by a computer bus. The device interface includes logic in support of a device management protocol to place the device interface in an unlocked state, a locked state to prevent changes to be made to the device interface, or an operational state to enable access to device registers of the device by the VM or direct memory access to memory address spaces of the VM, or an error state. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 21, 2020
    Inventors: Vedvyas Shanbhogue, Utkarsh Y. Kakaiya, Ravi Sahita, Abhishek Basak, Pradeep Pappachan, Erdem Aktas
  • Publication number: 20200155366
    Abstract: A disposable absorbent article may include a chassis that includes a topsheet, a backsheet, and an absorbent core disposed between the topsheet and the backsheet; and a leg gasketing system and a waist gasketing element. The leg gasketing system may include an inner cuff and an outer cuff; the inner cuff may include an inner cuff folded edge and an inner cuff material edge and the outer cuff may include an outer cuff folded edge and an outer cuff material edge such that the web of material is folded laterally inward to form the outer cuff folded edge and folded laterally outward to form the inner cuff folded edge. The leg gasketing system may also include a leg gasketing system pocket with an opening on an inboard longitudinal edge of the pocket.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: Jeromy Thomas Raycheck, Abhishek Prakash Surushe, Zachary Aaron Freije, Cornelia Beate Martynus, Donald Carroll Roe, Andrew James Sauer, Christopher Erin Kiger, Sara Lyn Giovanni
  • Publication number: 20200161473
    Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.
    Type: Application
    Filed: September 17, 2017
    Publication date: May 21, 2020
    Inventors: Prashant MAJHI, Willy RACHMADY, Brian S. DOYLE, Abhishek A. SHARMA, Elijah V. KARPOV, Ravi PILLARISETTY, Jack T. KAVALIEROS
  • Publication number: 20200160819
    Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: October 21, 2019
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Sanjeev S. Jahagirdar, Tapan A. Ganpule, Anupama A. Thaploo, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • Publication number: 20200162915
    Abstract: A wireless network environment includes a plurality of access points, a wireless local area network (WLAN) controller, and a plurality of client devices. The client devices attempt to authenticate with the WLAN controller to gain access to wireless services provided by the WLAN controller and/or the access points. To authenticate with the WLAN controller, the WLAN controller obtains a request to establish a wireless network connection from one or more of the client devices. The WLAN controller then provides a response to the request. The response indicates whether the WLAN controller supports performing password-mapped simultaneous authentication of equals (SAE). The WLAN controller then obtains a message including a password-mapped identifier from the client device. The WLAN controller then establishes a connection with the client device based on the password obtained with password-mapped identifier mapping at WLC.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Abhishek Dhammawat, Sudhir Kumar Jain, Mansi Jain
  • Patent number: D886125
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 2, 2020
    Assignee: Innoplexus AG
    Inventors: Pawan Kumar, Dileep Dharma, Abhishek Dewadiga