Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190318004
    Abstract: A system for processing user requests provides for recommending products or services for an agent to offer a customer or potential customer. The system classifies a user request by an intent, and presents documentation to assist the agent in handling the request. The system further parses the user request to detect life events experienced by the user that may raise the prospect of the user's interest in other products or services. Based on the detected life events, a number of offers are presented to an agent for recommendation to the user.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Inventors: Abhishek Rohatgi, Marco Antonio Padron, Flaviu Gelu Negrean, Paul Andrew Tepper
  • Publication number: 20190317643
    Abstract: A digital assistant supported across devices such as smartphones, tablets, personal computers (PCs), wearable computing devices, game consoles, and the like is configured to interact with a productivity system so that various user experiences, content, or features that enhance a user's productivity can be integrated with the digital assistant and rendered as a native digital assistant user experience. The digital assistant is configured to actively participate with the user to set and achieve productivity goals for example, by determining the user's intent, maintaining awareness of context, performing tasks and actions, providing productivity status and notifications, and interacting with the user to help the user stay productive and avoid distractions.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 17, 2019
    Inventors: Abhishek BHARDWAJ, Aditya VEGESNA, Anuja Chetan SHAH, Arnold Paul PEREIRA, Chaitanya Krishna DONTHINI, Gautam DAMBEKODI NAVINCHAND, Sachit MUCKADEN, Shefali VOHRA, Vignesh SHENOY, Yuvek Lokesh MEHTA
  • Publication number: 20190317851
    Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Om RANJAN, Riccardo GEMELLI, Abhishek GUPTA
  • Publication number: 20190318479
    Abstract: Disclosed are example embodiments of methods and systems for identifying and quantifying manufacturing defects of a manufactured dental prosthesis. Certain embodiments of the system for performing quality control on manufactured dental prostheses includes: a quality control module configured to determine whether the dental prosthesis is a good or a defective product based at least on a differences model generated by comparing a design model and a scanned model of the manufactured dental prosthesis.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Inventors: Abhishek Babasaheb Ajri, Vaheh Golestanian Nemagrdi, Marco Antonio Jokada, David Christopher Leeson
  • Publication number: 20190317771
    Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • Publication number: 20190319681
    Abstract: An apparatus for simultaneous transmit and receive is provided. The apparatus is capable of rejecting or passing transmitter and receiver signals. The apparatus includes: a transmitter; an antenna (e.g., a shared antenna); a receiver including switches controllable by time varying signals; and a quadrature coupler including first, second, third, and fourth ports, wherein the first port is coupled to the transmitter, wherein the second port is coupled to the antenna, and wherein the third and fourth ports are coupled to the receiver.
    Type: Application
    Filed: April 18, 2018
    Publication date: October 17, 2019
    Applicant: Oregon State University
    Inventors: Arun NATARAJAN, Abhishek AGRAWAL, Sanket JAIN, Robin GARG
  • Publication number: 20190313895
    Abstract: Machine learning algorithms are applied to OCT scan image data of a patient's retina to assess various eye diseases of the patient, such as ARMD, glaucoma, and diabetic retinopathy. The classification modules for each tested-for disease or condition preferably comprises an ensemble of machine learning algorithms, preferably including both deep learning and traditional machine learning (non-deep learning) algorithms. The results of the analysis can be transmitted back to the facility of the caregiver that used the OCT scanner to scan the patient's retina while the patient is still present at the caregiver's facility for an appointment.
    Type: Application
    Filed: November 21, 2017
    Publication date: October 17, 2019
    Inventors: James Hayashi, Ravi Starzl, Hugo Angulo, Abhishek Kar, Ramesh Oswal, Diego Penafiel, Weidong Yaun
  • Publication number: 20190318550
    Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: BARATH LAKSHAMANAN, LINDA l. HURD, BEN J. ASHBAUGH, ELMOUSTAPHA OULD-AHMED-VALL, LIWEI MA, JINGYI JIN, JUSTIN E. GOTTSCHLICH, CHANDRASEKARAN SAKTHIVEL, MICHAEL S. STRICKLAND, BRIAN T. LEWIS, LINDSEY KUPER, ALTUG KOKER, ABHISHEK R. APPU, PRASOONKUMAR SURTI, JOYDEEP RAY, BALAJI VEMBU, JAVIER S. TUREK, NAILA FAROOQUI
  • Publication number: 20190318446
    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 17, 2019
    Inventors: JOYDEEP RAY, ABHISHEK R. APPU, ALTUG KOKER, BALAJI VEMBU
  • Publication number: 20190318082
    Abstract: Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Applicant: INTEL CORPORATION
    Inventors: ABHISHEK BASAK, RAVI SAHITA, VEDVYAS SHANBHOGUE
  • Publication number: 20190317899
    Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).
    Type: Application
    Filed: April 25, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: Altug Koker, Joydeep Ray, James A. Valerio, Abhishek R. Appu, Vasanth Ranganathan
  • Patent number: 10445923
    Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Devan Burke, Abhishek Venkatesh, Travis Schluessler
  • Patent number: 10444809
    Abstract: In various examples, a system comprises a rack-mountable power distribution unit (PDU). The PDU may: receive an alternating current (AC) power feed, convert the AC to a direct current (DC) power pool, determine an amount of available amount of power of the DC power pool to be delivered to devices electrically coupled to the PDU, and output the DC power pool to the devices coupled to the PDU based on the amount of available power.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: October 15, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Abhishek Banerjee, Matthew E. Stevens
  • Patent number: 10444817
    Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Altug Koker, Abhishek R. Appu, Bhushan M. Borole, Wenyin Fu, Kamal Sinha, Joydeep Ray
  • Patent number: 10444490
    Abstract: A display device including a first support plate and an opposing second support plate. A first pixel is positioned between the first support plate and the second support plate. A spacer structure is coupled to the second support plate and associated with the first pixel. The spacer structure allows propagation of light having a first wavelength and prevents propagation of light having a second wavelength.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Tulasi Sridhar Reddy Guntaka, Toru Sakai, Abhishek Kumar, Karel Johannes Gerhardus Hinnen
  • Patent number: 10447047
    Abstract: An apparatus includes a plurality of energy storage modules (ESMs) to store charge. Each ESM includes module inputs to receive the charge. A plurality of charging circuits supply electrical energy to charge the ESMs via an output from each of the charging circuits. A switch network selectively switches each of the outputs from each of the charging circuits to the respective module inputs of each of the ESMs in response to a control command.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 15, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Hai Nguyen, Abhishek Banerjee
  • Patent number: 10447253
    Abstract: A high performance phase-locked loop, the device includes a phase frequency detector, a charge pump, a loop filter, a first oscillator having inverters, configured to generate a first current, a second oscillator having a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 15, 2019
    Assignee: MegaChips Corporation
    Inventor: Abhishek Kumar Khare
  • Patent number: 10448121
    Abstract: An online system presents content in videos to users. Content providers may value having their content injected into videos from certain sources more than others. This preference is quantified as a brand value score. The brand value score is determined as a function of user engagement with a source of the video and, to account for brand value, the system performs a two-stage auction. First, the system determines whether to inject any content into a video by determining a distribution of brand value of videos per demand for videos in a previous period and filling a projected demand for the content in a current period to determine a brand value threshold. Then, any videos having a brand value above the threshold are eligible for the second stage of the selection process where the system performs an auction where projected benefit of presenting the content is compared to projected loss.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: October 15, 2019
    Assignee: Facebook, Inc.
    Inventor: Abhishek Bapna
  • Patent number: 10445745
    Abstract: A computerized method of representing customer interactions with an organization includes: receiving, by a computing device, customer web interaction data segments and customer conversation data segments; pre-processing the customer conversation data segments to remove specified types of information; scoring each of the pre-processed customer conversation data segments; pre-processing the customer web data interaction segments; extracting from the pre-processed customer web interaction data segments tokens; combining the pre-processed customer conversation data segments and the pre-processed customer web interaction data segments into a customer data set; parsing the customer data set into one or more windows; assigning, for each window, pre-trained weights to each of the tokens in each window; assigning a transaction theme to each window based on the tokens in each window; and generating, based on the transaction themes, a ranked list of topic keywords reflecting the customer web interaction data segments an
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 15, 2019
    Assignee: FMR LLC
    Inventors: Ankush Chopra, Abhishek Desai, Aravind Chandramouli
  • Publication number: 20190310558
    Abstract: Methods and apparatus for processing an image of a beam generated by an optical system to extract information indicative of an extent of damage to optical elements in the optical system. Also disclosed is a beam image and analysis tool capable of acquiring an image of a beam at any one of a number of locations.
    Type: Application
    Filed: June 13, 2019
    Publication date: October 10, 2019
    Inventors: Thomas Frederick Allen Bibby, JR., Omar Zurita, Abhishek Subramanian, Thomas Patrick Duffey