Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DETERMINGING ROOT CAUSE OF LOCOMOTIVE FAILURE
    Publication number: 20180312180
    Abstract: The example embodiments are directed to a device and method for determining a root cause of equipment failure. In one example, the method includes storing a plurality of root causes of previous equipment failures, receiving textual data associated with a current equipment failure, determining a root cause for the current equipment failure by determining a similarity of keywords of each root cause with respect to the received textual data of the current equipment failure and selecting at least one root cause based on the determined similarities of the plurality of root causes, and displaying the at least one determined root cause for the current equipment failure via a display device. The example embodiments provide a system and method that automatically determine a root cause of equipment failure rather than rely on a subject matter expert.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Chris J. WANG, Abhishek NARAIN, Vikram LAKSHMIPATHY
  • STORAGE MANAGEMENT FOR MACHINE LEARNING AT AUTONOMOUS MACHINES
    Publication number: 20180314249
    Abstract: A mechanism is described for facilitating storage management for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting one or more components associated with machine learning, where the one or more components include memory and a processor coupled to the memory, and where the processor includes a graphics processor. The method may further include allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, where the storage and hardware portions are precise for implementation and processing of the training set.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, John C. Weast, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Altug Koker, Farshad Akhbari, Feng Chen, Dukhwan Kim, Narayan Srinivasa, Nadathur Rajagopalan Satish, Kamal Sinha, Joydeep Ray, Balaji Vembu, Mike B. Macpherson, Linda L. Hurd, Sanjeev Jahagirdar, Vasanth Ranganathan
  • INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING
    Publication number: 20180315399
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
    Type: Application
    Filed: November 21, 2017
    Publication date: November 1, 2018
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Technologies for determining sensor deployment characteristics
    Patent number: 10116530
    Abstract: Systems, methods, and computer-readable media for detecting sensor deployment characteristics in a network. In some embodiments, a system can run a capturing agent deployed on a virtualization environment of the system. The capturing agent can query the virtualization environment for one or more environment parameters, and receive a response from the virtualized environment including the one or more environment parameters. Based on the one or more environment parameters, the capturing agent can determine whether the virtualization environment where the capturing agent is deployed is a hypervisor or a virtual machine. The capturing agent can also determine what type of software switch is running in the virtualized environment.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: October 30, 2018
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Navindra Yadav, Abhishek Ranjan Singh, Anubhav Gupta, Shashidhar Gandham, Jackson Ngoc Ki Pang, Shih-Chun Chang, Hai Trong Vu
  • Distributed workload management
    Patent number: 10115071
    Abstract: Examples of distributed workload management are disclosed. In one example implementation according to aspects of the present disclosure, a partial data table is received from a main data table. A data view is generated in real time in response to a received data view request. The data view is based at least in part on a plurality of data view configuration properties and the partial data stored in the received partial data table. The partial data table stores data that represents at least a partial copy of main data stored in a main data table. The partial data table and the main data table are then synchronized.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 30, 2018
    Assignee: Manhattan Associates, Inc.
    Inventors: Kayla Elizabeth Amaral, Anup K. G, Shashikala Maracharahalli Bhadraiah, Abhishek Jain, Suhas Prahlada Rao, Ranjith Krishnan Nadar, Vikas Aron, Baibhav Singh
  • Information storage system
    Patent number: 10114691
    Abstract: Provided is an information storage system including a first storage apparatus configured to provide a first logical volume, a second storage apparatus configured to provide a second logical volume, and a quorum accessed from the first storage apparatus and the second storage apparatus and including information regarding states of the first storage apparatus and the second storage apparatus. The second storage apparatus is configured to, after detecting communication failure with the quorum, halt use of the quorum and check communication with the first storage apparatus for failure before responding to the host for each of read and write commands sent from the host.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: October 30, 2018
    Assignee: HITACHI, LTD.
    Inventors: Abhishek Johri, Takahito Sato, Hideo Saito, Tomohiro Kawaguchi
  • Thin-film devices and fabrication
    Patent number: 10114265
    Abstract: Thin-film devices, for example electrochromic devices for windows, and methods of manufacturing are described. Particular focus is given to methods of patterning optical devices. Various edge deletion and isolation scribes are performed, for example, to ensure the optical device has appropriate isolation from any edge defects. Methods described herein apply to any thin-film device having one or more material layers sandwiched between two thin film electrical conductor layers. The described methods create novel optical device configurations.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: October 30, 2018
    Assignee: View, Inc.
    Inventors: Fabian Strong, Yashraj Bhatnagar, Abhishek Anant Dixit, Todd Martin, Robert T. Rozbicki
  • Communication between devices of a neighbor aware network
    Patent number: 10117222
    Abstract: In some examples, a method includes receiving, at a second device of a data link group of a neighbor aware network (NAN), a message including an indication of whether a first device corresponding to a particular service is available during a particular time period during which devices of the data link group are configured to operate in an active operating mode. The method also includes transitioning to a low-power operating mode during one or more transmission windows corresponding to the particular time period in response to determining that the first device is unavailable during the particular time period.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Abhishek Pramod Patil, Santosh Paul Abraham, George Cherian, Alireza Raissinia, James Cho, Guido Frederiks
  • Round trip time (RTT) measurement based upon sequence number
    Patent number: 10116531
    Abstract: Systems, methods, and computer-readable media are provided for determining a packet's round trip time (RTT) in a network. A system can receive information of a packet sent by a component of the network and further determine an expected acknowledgement (ACK) sequence number associated with the packet based upon received information of the packet. The system can receive information of a subsequent packet received by the component and determine an ACK sequence number and a receiving time of the subsequent packet. In response to determining that the ACK sequence number of the subsequent TCP packet matches the expected ACK sequence number, the system can determine a round trip time (RTT) of the packet based upon the received information of the packet and the received information of the subsequent packet.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 30, 2018
    Assignee: CISCO TECHNOLOGY, INC
    Inventors: Mohammadreza Alizadeh Attar, Navindra Yadav, Abhishek Ranjan Singh, Vimalkumar Jeyakumar, Shashidhar Gandham, Roberto Fernando Spadaro
  • COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
    Publication number: 20180308200
    Abstract: An apparatus to facilitate compute optimization is disclosed.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • POSITIONAL ONLY SHADING PIPELINE (POSH) GEOMETRY DATA PROCESSING WITH COARSE Z BUFFER
    Publication number: 20180308277
    Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
  • DOOR WITH FRAMELESS GLAZED UNIT, AND RELATED KIT AND METHODS
    Publication number: 20180305971
    Abstract: A door includes a door frame, first and second door skins having rectangular outer peripheries and inner openings, and a frameless glazed unit received at the openings. The door skins include exterior surfaces facing away from the door frame and opposite interior surfaces facing and secured to opposite sides of the door frame. The exterior and interior surfaces of the first and second door skins establish integral lips and grooves of the first and second door skins Opposite sides of the frameless glazed unit directly contact and are sealed by the integral lips and sealant and/or adhesive contained in the grooves of the first and second door skins.
    Type: Application
    Filed: June 26, 2018
    Publication date: October 25, 2018
    Inventors: Timothy D. GOUGE, Abhishek Vaidya, Robert C. ALLEN, Steven B. SWARTZMILLER, Jason M. WALSH
  • COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURING INFERENCE
    Publication number: 20180308202
    Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Linda L. Hurd, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Liwei Ma, Elmoustapha Ould-Ahmed-Vall, Kamal Sinha, Joydeep Ray, Balaji Vembu, Sanjeev Jahagirdar, Vasanth Ranganathan, DUKHWAN Kim
  • HDR ENHANCEMENT WITH TEMPORAL MULTIPLEX
    Publication number: 20180308269
    Abstract: Systems, apparatuses and methods may a performance-enhanced computing system comprising a sensor for measuring luminance values corresponding to light focused onto the sensor at a plurality of pixel locations, a memory including a set of instructions, and a processor. The processor executes a set of instructions causing the system to generate a multi-segment tone mapping curve, generate a set of tone mapping values corresponding to the multi-segment tone mapping curve for equally spaced input values between zero and one for storage into a look up table, and process the luminance values using the look up table to apply the tone mapping curve to the luminance values of the pixels.
    Type: Application
    Filed: June 5, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Stanley J. Baran, Abhishek R. Appu, Sang-Hee Lee, Atthar H. Mohammed, Jong Dae Oh, Hiu-Fai R. Chan, Joydeep Ray, Kunjal Parikh, Changliang Wang, Srikanth Kambhatla, Gary Smith, Satyanarayana Avadhanam, Richmond Hicks, Robert J. Johnston, Narayan Biswal, Susanta Bhattacharjee
  • DYNAMIC THREAD EXECUTION ARBITRATION
    Publication number: 20180308196
    Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Subramaniam M. Maiyuran, Eric J. Hoekstra, Prasoonkumar Surti, Balaji Vembu, Altug Koker
  • COMPUTE CLUSTER PREEMPTION WITHIN A GENERAL-PURPOSE GRAPHICS PROCESSING UNIT
    Publication number: 20180308209
    Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD
    Publication number: 20180310113
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Joydeep Ray, Travis T. Schluessler, Prasoonkumar Surti, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, James M. Holland, Jeffery S. Boles, Jonathan Kennedy, Louis Feng, Atsuo Kuwahara, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • MEMORY ACCESS COMPRESSION USING CLEAR CODE FOR TILE PIXELS
    Publication number: 20180307621
    Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Kiran C. Veernapu
  • INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION
    Publication number: 20180307295
    Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Mohammed Tameem, Altug Koker, Kiran C. Veernapu, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Travis T. Schluessler, Jonathan Kennedy
  • RECOGNITION, REIDENTIFICATION AND SECURITY ENHANCEMENTS USING AUTONOMOUS MACHINES
    Publication number: 20180307899
    Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corproation
    Inventors: Barnan Das, MAYURESH M. VARERKAR, NARAYAN BISWAL, STANLEY J. BARAN, GOKCEN CILINGIR, NILESH V. SHAH, ARCHIE SHARMA, SHERINE ABDELHAK, Praneetha Kotha, Neelay Pandit, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Abhishek R. Appu, Altug Koker, Joydeep Ray