Abstract: According to one aspect of the invention, a method is provided in which a first clock signal is generated. A second clock signal is derived from the first clock signal. The second clock signal is delayed relative to the first clock signal by a first delay period by a delay locked loop (DLL) circuit. The second clock signal is used to latch incoming data from a memory device.

Abstract: According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Abstract: According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Abstract: According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Abstract: A method and apparatus for efficiently controlling the access to a cached shared resource such as dynamic random access memory (DRAM). The access is effected in a pseudo-concurrent manner by two devices such as a central processing unit (CPU) and a bus master agent. While one device accesses data stored in the DRAM, the other device accesses a copy of the DRAM data which is stored in the cache of the shared resource.

Abstract: A dynamic cache coherency method and apparatus providing enhanced microprocessor system performance are described. The method and apparatus are advantageously utilized in a microprocessor system comprising a central processing unit (CPU), a write back cache memory, dynamic random access memory (DRAM) main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer. In accordance with the method of operation, following a write access by the CPU, the CDC determines whether the write buffer is full and whether the cache line associated with this access has been modified, i.e. is "clean" or "dirty." In the event that the write buffer is full, or the cache line is dirty, the write operation proceeds in accordance with a write back mode of operation. However, if the write buffer in the DPU is not full, and the cache line is clean, the CDC writes the write data to both the cache line in cache memory, and the write buffer in the DPU.