Patents by Inventor Abishek Gopalan

Abishek Gopalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230231628
    Abstract: The present disclosure provides systems and methods for operating optical networks and performing defragmentation operations. Embodiments include computer systems and computer program products comprising a computer readable storage and a processor. Upon receiving information indicative of a spectrum assignment on the optical network, a target entity associated with a set of optical channels and a potential spectrum path are identified. The target entity can be defragmented to enable the potential spectrum path, comprising reconfiguring at least one existing spectrum path associated with an optical channel in the set of optical channels. The potential spectrum path may then be reconfigured to a continuous and contiguous band of slice on at least one optical channel associated with the target entity.
    Type: Application
    Filed: January 14, 2022
    Publication date: July 20, 2023
    Inventors: Satyajeet Singh Ahuja, Srivatsan Balasubramanian, Vinayak Dangui, Abishek Gopalan
  • Patent number: 11252029
    Abstract: The disclosed computer-implemented method may include (i) generating a data center constraint model by placing a constraint on a total amount of ingress or egress traffic a service expects from each respective data center of multiple data centers, (ii) filtering a set of traffic matrices that indicate points in the data center constraint model by comparing the set of traffic matrices against cut sets of a network topology that indicate network failures to create a tractable set of dominating traffic matrices, (iii) obtaining physical network resources to implement a cross-layer network upgrade architecture that satisfies the tractable set of dominating traffic matrices, and (iv) allocating the physical network resources across the multiple data centers according to the cross-layer network upgrade architecture such that a capacity level of the multiple data centers is increased while satisfying the data center constraint model. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: February 15, 2022
    Assignee: Facebook, Inc.
    Inventors: Satyajeet Singh Ahuja, Varun Gupta, Vinayak Dangui, Soshant Bali, Gayathrinath Nagarajan, Petr V Lapukhov, Hao Zhong, Ying Zhang, Abishek Gopalan
  • Patent number: 11184248
    Abstract: A method and system for allocating network resources are described. The method includes receiving a plurality of forecasted network traffic patterns for a network. A representative subset of the plurality of forecasted network traffic patterns is selected based on an analysis of the plurality of forecasted network traffic patterns using a topology of the network. The selected representative subset of the plurality of forecasted network traffic patterns is used to determine a resource allocation for the network.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: November 23, 2021
    Assignee: Facebook, Inc.
    Inventors: Satyajeet Singh Ahuja, Abishek Gopalan, Vinayak Dangui, Gayathrinath Nagarajan, Petr V. Lapukhov
  • Patent number: 10917363
    Abstract: An optimized communication network may include an edge switch capable of transporting and switching L1 and L2 traffic and configured to selectively transport and switch L2 traffic using L1 protocols.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 9, 2021
    Assignee: Infinera Corporation
    Inventors: Abishek Gopalan, Snigdho Bardalai, Biao Lu, Onur Turkcu, Parthiban Kandappan
  • Patent number: 10587500
    Abstract: Memory devices, methods and systems are described in which a non-transitory memory device stores instructions that, when executed by a processor, cause the processor to: receive, via an input component, at least one message from a network element in a multi-layer network comprising information indicative of at least one failure of a working path; determine based at least in part on information indicative of a data transport path coincident with the working path in a second layer in the network different from the first layer, an alternate path in the first layer for transmission of the data through the multi-layer network; and transmit, via an output component, at least one signal comprising configuration instructions to at least one line module, the configuration instructions directing the line module to switch and transmit the data using the alternate path.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 10, 2020
    Assignee: Infinera Corporation
    Inventors: Abishek Gopalan, Rajan Rao, Biao Lu
  • Publication number: 20170295090
    Abstract: Memory devices, methods and systems are described in which a non-transitory memory device stores instructions that, when executed by a processor, cause the processor to: receive, via an input component, at least one message from a network element in a multi-layer network comprising information indicative of at least one failure of a working path; determine based at least in part on information indicative of a data transport path coincident with the working path in a second layer in the network different from the first layer, an alternate path in the first layer for transmission of the data through the multi-layer network; and transmit, via an output component, at least one signal comprising configuration instructions to at least one line module, the configuration instructions directing the line module to switch and transmit the data using the alternate path.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 12, 2017
    Inventors: Abishek Gopalan, Rajan Rao, Biao Lu
  • Publication number: 20170093705
    Abstract: A method for determining a path through a communication network may include determining a first and second path from a first device to a second device based on path latency, removing from further consideration the first or the second path based on which has the highest path latency of the first and second path, and determining path candidates until a path candidate is found with the lowest differential latency between the determined first or second path and the path candidate.
    Type: Application
    Filed: December 31, 2015
    Publication date: March 30, 2017
    Inventors: Abishek GOPALAN, Biao LU, Rajan RAO
  • Patent number: 9548944
    Abstract: A switch network may include a plurality of switch stages arranged in sequential stages. The plurality of switch stages may include a first switch stage connected to a plurality of inputs, a second switch stage connected to each switch in the first switch stage, a third switch connected to each switch in the second switch stage, a fourth switch stage connected to each of the switches in the third switch stage, and a fifth switch stage connected to a plurality of outputs and each switch in the fourth switch stage, and a control element configured to control each of the plurality of switch stages for routing a signal from one of the plurality of inputs to one of the plurality of outputs.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: January 17, 2017
    Assignee: Infinera Corporation
    Inventors: Abishek Gopalan, Biao Lu
  • Publication number: 20160373205
    Abstract: An optimized communication network may include an edge switch capable of transporting and switching L1 and L2 traffic and configured to selectively transport and switch L2 traffic using L1 protocols.
    Type: Application
    Filed: September 30, 2015
    Publication date: December 22, 2016
    Inventors: Abishek GOPALAN, Snigdho BARDALAI, Biao LU, Onur TURKCU, Parthiban KANDAPPAN
  • Publication number: 20150244647
    Abstract: A switch network may include a plurality of switch stages arranged in sequential stages. The plurality of switch stages may include a first switch stage connected to a plurality of inputs, a second switch stage connected to each switch in the first switch stage, a third switch connected to each switch in the second switch stage, a fourth switch stage connected to each of the switches in the third switch stage, and a fifth switch stage connected to a plurality of outputs and each switch in the fourth switch stage, and a control element configured to control each of the plurality of switch stages for routing a signal from one of the plurality of inputs to one of the plurality of outputs.
    Type: Application
    Filed: June 11, 2014
    Publication date: August 27, 2015
    Inventors: Abishek Gopalan, Biao Lu