Abstract: Rechargeable wafer carrier systems and methods are provided. A rechargeable wafer carrier system includes, for instance, a housing for holding at least one wafer and at least one electronics system therein, a rechargeable power source operably connected to the housing for powering the at least one electronics system, and a charging interface for receiving a supply of power for charging the rechargeable power source. The housing may be configured for transport within an automated material handling system. Also provided are methods of charging a rechargeable wafer carrier system, which includes, for instance, providing a rechargeable wafer carrier system having at least one electronics system and a rechargeable power source, operably connecting the rechargeable wafer carrier system to a charging base, and supplying power from the charging base to the rechargeable power source.

Abstract: Self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers. The wafer carrier system may include a housing configured for transport within the automated material handling system. A support is configured to support a semiconductor wafer within a housing. A metrology system is disposed within the housing. The metrology system is operable to measure at least one characteristic of the wafer. The metrology system may include a sensing unit and a computing unit operably connected to the sensing unit.

Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.

Abstract: Self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers. The wafer carrier system may include a housing configured for transport within the automated material handling system. A support is configured to support a semiconductor wafer within a housing. A metrology system is disposed within the housing. The metrology system is operable to measure at least one characteristic of the wafer. The metrology system may include a sensing unit and a computing unit operably connected to the sensing unit.

Abstract: A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier system includes, for instance, a housing configured for transport within the automated material handling system, the housing having a support configured to support a semiconductor wafer in the housing, and a metrology system disposed within the housing, the metrology system operable to measure at least one characteristic of the wafer, the metrology system comprising a sensing unit and a computing unit operably connected to the sensing unit. Also provided are methods of measuring one or more characteristics of a semiconductor wafer within the wafer carrier systems of the present disclosure.

Abstract: A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier system includes, for instance, a housing configured for transport within the automated material handling system, the housing having a support configured to support a semiconductor wafer in the housing, and a metrology system disposed within the housing, the metrology system operable to measure at least one characteristic of the wafer, the metrology system comprising a sensing unit and a computing unit operably connected to the sensing unit. Also provided are methods of measuring one or more characteristics of a semiconductor wafer within the wafer carrier systems of the present disclosure.

Abstract: A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier system includes, for instance, a housing configured for transport within the automated material handling system, the housing having a support configured to support a semiconductor wafer in the housing, and a metrology system disposed within the housing, the metrology system operable to measure at least one characteristic of the wafer, the metrology system comprising a sensing unit and a computing unit operably connected to the sensing unit. Also provided are methods of measuring one or more characteristics of a semiconductor wafer within the wafer carrier systems of the present disclosure.

Abstract: Rechargeable wafer carrier systems and methods are provided. A rechargeable wafer carrier system includes, for instance, a housing for holding at least one wafer and at least one electronics system therein, a rechargeable power source operably connected to the housing for powering the at least one electronics system, and a charging interface for receiving a supply of power for charging the rechargeable power source. The housing may be configured for transport within an automated material handling system. Also provided are methods of charging a rechargeable wafer carrier system, which includes, for instance, providing a rechargeable wafer carrier system having at least one electronics system and a rechargeable power source, operably connecting the rechargeable wafer carrier system to a charging base, and supplying power from the charging base to the rechargeable power source.

Abstract: A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier system includes, for instance, a housing configured for transport within the automated material handling system, the housing having a support configured to support a semiconductor wafer in the housing, and a metrology system disposed within the housing, the metrology system operable to measure at least one characteristic of the wafer, the metrology system comprising a sensing unit and a computing unit operably connected to the sensing unit. Also provided are methods of measuring one or more characteristics of a semiconductor wafer within the wafer carrier systems of the present disclosure.

Abstract: A method of straining fins of a FinFET device by using a stress memorization film and the resulting device are provided. Embodiments include providing a plurality of bulk Si fins, the plurality of bulk Si fins having a recessed oxide layer therebetween; forming a stress memorization layer over the plurality of bulk Si fins and the recessed oxide layer; annealing the stress memorization layer, the plurality of bulk Si fins, and the recessed oxide layer; and removing the stress memorization layer.

Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fin-formation trenches that define a fin, forming a first stressed layer within the trenches and above the fin and performing at least one etching process on the first stressed layer so as to define spaced-apart portions of the first stressed layer positioned at least partially within the trenches on opposite sides of the fin. The method also includes forming spaced-apart portions of a second stressed layer above the spaced-apart portions of the first layer, forming a third stressed layer above the fin between the spaced-apart portions of the second layer and, after forming the third layer, forming a conductive layer above the second and third layers.

Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first surface. In the method, a stress is applied to the semiconductor substrate to change inter-atomic spacing at the first surface of the semiconductor substrate to a stressed inter-atomic spacing. Then, the semiconductor substrate is processed. Thereafter, the stress is released and the first surface of the processed semiconductor substrate retains the stressed inter-atomic spacing.