Patents by Inventor Abnijeet A. Chachad

Abnijeet A. Chachad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Highly Integrated Scalable, Flexible DSP Megamodule Architecture
    Publication number: 20150019840
    Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 15, 2015
    Inventors: Timothy D. Anderson, Joseph Zbiciak, Duc Quang Bui, Abnijeet A. Chachad, Kai Chirca, Naveen Bhoria, Matthew D. Pierson, Daniel Wu