Abstract: Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink.

Abstract: An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are provided. In one embodiment, an interposer is provided that includes an interconnect layer disposed on a substrate. A plurality of through-vias are formed through the substrate in an isolated region of the substrate. At least one of the plurality of conductive vias are electrically coupled to at least one of a plurality of top wires formed in the interconnect layer. A plurality of blind-vias are formed through the substrate in a dense region of the substrate during a common etching step with the through-vias. At least one blind-via includes (a) a dielectric material lining the blind-vias, and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.

Abstract: An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.

Abstract: A method for controlling a semiconductor fabrication process includes the steps of analyzing process-data related to an intermediate-process-step in the fabrication process and adjusting a metal-layer-parameter corresponding to the metal layer based on the process-data.

Abstract: An integrated circuit system includes a heat spreader that is thermally coupled to a semiconductor chip and has a cavity or opening formed in the heat spreader. The cavity or opening is positioned so that capacitors and/or other passive components mounted to the same packaging substrate as the semiconductor chip are at least partially disposed in the cavity or opening. Because the passive components are disposed in the cavity or opening, the integrated circuit system has a reduced package thickness.

Abstract: Embodiments of the invention generally relate to interposers for packaging integrated circuits. The interposers include capacitive devices for reducing signal noise and leakage between adjacent integrated circuits coupled to the interposers. The capacitive devices are formed from doped semiconductor layers. In one embodiment, an interposer includes a substrate having doped regions of opposing conductivities. First and second oxide layers are disposed over the doped regions. A first interconnect disposed in the second oxide layer is electrically coupled to a doped region of a first conductivity, and a second interconnect disposed in the second oxide is electrically coupled to a doped region of a second conductivity. Additional capacitive devices utilizing doped semiconductor layers are also disclosed.

Abstract: One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication.

Abstract: A system, method, and computer program product are provided for affixing a post to a substrate pad. In use, a post is affixed to each of one or more pads of a substrate, where each post receives a ball of a package during an assembly process.

Abstract: An integrated circuit package includes an interposer and an integrated circuit die. The interposer is formed from a layer of semiconductor material that is separated from a bulk portion of a semiconductor substrate, and the integrated circuit die is coupled to the interposer. Vias in the interposer can be formed in the thin layer of semiconductor material removed from the semiconductor substrate, and therefore can be scaled down significantly in size. Such reduced-size, through-interposer vias can be etched and filled much more cost-effectively and result in greatly reduced parasitic capacitance in the integrated circuit package.

Abstract: An integrated circuit package includes an integrated circuit package comprising an interposer and an integrated circuit die. The interposer is formed from a silicon-on-insulator semiconductor substrate and includes a plurality of through-silicon vias, and the integrated circuit die is electrically coupled to a first through-silicon via included in the plurality of through-silicon vias. Through-silicon vias in the integrated circuit package can be formed in the thin silicon surface layer of the silicon-on-insulator substrate, and therefore can be scaled down significantly in size. Such reduced-size through-silicon vias can be etched and filled much more cost-effectively and result in greatly reduced parasitic capacitance in the integrated circuit package.

Abstract: An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are provided. In one embodiment, an interposer is provided that includes an interconnect layer disposed on a substrate. A plurality of through-vias are formed through the substrate in an isolated region of the substrate. At least one of the plurality of conductive vias are electrically coupled to at least one of a plurality of top wires formed in the interconnect layer. A plurality of blind-vias are formed through the substrate in a dense region of the substrate during a common etching step with the through-vias. At least one blind-via includes (a) a dielectric material lining the blind-vias, and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.

Abstract: One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication.

Abstract: An integrated circuit system includes an interposer substrate with an electrical reference plane, or “ground plane,” formed by a conductive semiconductor layer. The conductive semiconductor layer may be formed in a surface region of the interposer substrate, and in some embodiments is formed by performing an ion implant process on the surface region to increase the electrical conductivity of the surface region. Because the surface region is electrically coupled to an electrical ground of the integrated circuit system, the surface region functions as a ground plane that helps contain electric fields produced by signals routed through interconnects of the interposer substrate. Consequently, a ground plane can be formed on a surface of the interposer substrate without forming a metalization layer.

Abstract: An integrated circuit system includes a heat spreader that is thermally coupled to a semiconductor chip and has a cavity or opening formed in the heat spreader. The cavity or opening is positioned so that capacitors and/or other passive components mounted to the same packaging substrate as the semiconductor chip are at least partially disposed in the cavity or opening. Because the passive components are disposed in the cavity or opening, the integrated circuit system has a reduced package thickness.

Abstract: Embodiments of the present invention include devices having multiple dies packaged together in the same package. The multiple dies are disposed on an interposer which is then disposed on a package substrate. The interposer includes a semiconductor substrate, such as silicon, having vias extending from a front surface of the interposer to a back surface of the interposer. The interposer may be a passive interposer or an active poser. An active interposer includes the functionality of one or more dies and thus reduces the number of dies disposed on the active interposer.

Abstract: One embodiment of the present invention sets forth a processing module including an interposer and a plurality of processing nodes. The interposer includes a plurality of through substrate vias. Each processing node includes a processing unit die coupled directly to a top surface of the interposer with a first plurality of solder bump structures, a memory die coupled directly to the top surface of the interposer with a second plurality of solder bump structures, and a plurality of circuit elements electrically coupling the processing unit die and the memory die. The processing module further includes a plurality of electrical connections formed on a bottom surface of the interposer and electrically coupled to the plurality of processing nodes through the plurality of through substrate vias. The processing module further comprises a plurality of interconnecting circuit elements electrically interconnecting the plurality of processing nodes.

Abstract: Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink.

Abstract: Embodiments of the invention provide an IC system in which low-power chips can be positioned proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system may include a first substrate, a high-power chip embedded within the first substrate, a second substrate disposed on a first side of the first substrate, the first substrate and the second substrate are in electrical communication with each other, and a low-power chip disposed on the second substrate. In various embodiments, a heat distribution layer is disposed adjacent to the high-power chip such that the heat generated by the high-power chip can be effectively dissipated into an underlying printed circuit board attached to the first substrate, thereby preventing heat transfer from the high-power chip to the low-power chip. Therefore, the lifetime of the low-power chip is extended.

Abstract: Embodiments of the invention generally relate to interposers for packaging integrated circuits. The interposers include capacitive devices for reducing signal noise and leakage between adjacent integrated circuits coupled to the interposers. The capacitive devices are formed from doped semiconductor layers. In one embodiment, an interposer includes a substrate having doped regions of opposing conductivities. First and second oxide layers are disposed over the doped regions. A first interconnect disposed in the second oxide layer is electrically coupled to a doped region of a first conductivity, and a second interconnect disposed in the second oxide is electrically coupled to a doped region of a second conductivity. Additional capacitive devices utilizing doped semiconductor layers are also disclosed.

Abstract: Embodiments of the present invention provide a packaging system, which generally includes a substrate, a first electrical conductive pad and a second electrical conductive pad formed on a top surface of the substrate, and a mask section formed on the top surface of the substrate and disposed between the first electrical conductive pad and the second electrical conductive pad. The packaging system further includes a passive component mounted onto a top surface of the mask section, wherein a portion of a back surface of the passive component is in physical contact with the first electrical conductive pad and the second electrical conductive pad, respectively.