Abstract: A receiver for a multi-carrier communication system receives training pilot carriers (TRPC) during a training symbol (T1, T2) which precedes data symbols (DS) which have data carriers (DC) and data pilot carriers (PC). The receiver has a correction unit (171) which supplies, under control of a control signal (CEC), a corrected signal (CDC1) which has the data carriers (DC) which are corrected for a common amplitude error and/or common phase error.

Abstract: A receiver circuit has a chain of stream processing circuits (10a-c)—having control parameter inputs for receiving control parameter values. To facilitate design of circuits that receive data with a variable block size, an included control circuit (14) selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (10a-c), a control parameter value for each particular block. The control circuit transmits instructions specifying the selected block sizes and control parameter values to local control circuits (11). Each local control circuit is coupled to the control circuit (14) and the control input of a respective corresponding stream processing circuit (10a-c). Each local control circuit (11) receives at least part of the instructions and applies parameter values from the instructions to its corresponding stream processing circuit (10a-c). The local control circuit (11) controls timing of control parameter updates using block sizes from the instructions.

Abstract: A receiver for a multi-carrier communication system has a channel corrector (173) which receives an input signal (CDC2) and a correction control signal (EC) to correct an amplitude and/or phase of the input signal (CDC2) to obtain a corrected signal (ED). A channel estimator (19) has a slicer (190) which performs a hard-decision on the corrected signal (ED) to obtain a decided signal (HDS). The correction control signal (EC) is dependent on a difference between the input signal (CDC2) and the decided signal (HDS) to decrease said difference.

Abstract: A local area network is provided where an OFDM station and DSSS/CCK station coexist. During a contention-free period both stations operate under the point coordination function rules as defined in the IEEE 802.11 specification. Both stations transmit data when polled by the access point. The contention-free period comprises a sub-contention period during which only the OFDM station communicate. During the sub-contention period the OFDM station operates under the distributed coordination function while the DSSS/CCK station waits to be polled by the access point before starting to communicate.

Abstract: An electronic circuit, in particular a receiver circuit contains a chain of stream processing circuits (10a-c). The stream processing circuits (10a-c) have control parameter inputs for receiving control parameter values. In order to facilitate design of circuits that receive data with a variable block size, a control circuit (14) is included that selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (10a-c), a control parameter value for each particular block. The control circuit transmits instructions that specify the selected block sizes and control parameter values to local control circuits (11). Each local control circuit is coupled to the control circuit (14) and the control input of a respective corresponding stream processing circuit (10a-c) from the chain.

Abstract: An electronic circuit, in particular a receiver circuit contains a chain of stream processing circuits (I0a-c). The stream processing circuits (IOa-c) have control parameter inputs for receiving control parameter values. In order to facilitate design of circuits that receive data with a variable block size, a control circuit (14) is included that selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (10a-c), a control parameter value for each particular block. The control circuit transmits instructions that specify the selected block sizes and control parameter values to local control circuits (11). Each local control circuit is coupled to the control circuit (14) and the control input of a respective corresponding stream processing circuit (10a-c) from the chain.

Abstract: A local area network is provided where OFDM stations and DSSS/CCK only stations coexist. Before transmitting, an OFDM station learns of the modulation capability of an intended receiving station. If the receiving station is only capable of DSSS/CCK modulation then the OFDM station transmits DSSS/CCK modulated data. If the receiving station is capable of OFDM modulation, then the OFDM station transmits OFDM modulated data thereby enabling efficient bandwidth usage.

Abstract: A local area network is provided where an OFDM station and DSSS/CCK station coexist. During a contention-free period both stations operate under the point coordination function rules as defined in the IEEE 802.11 specification. Both stations transmit data when polled by the access point. The contention-free period comprises a sub-contention period during which only the OFDM station communicate. During the sub-contention period the OFDM station operates under the distributed coordination function while the DSSS/CCK station waits to be polled by the access point before starting to communicate.

Abstract: In a transmission system for digital symbols, such as used for DVB, source symbols are encoded by a block coder (4), subjected to an interleaving operation in an interleaver and subsequently encoder in a channel encoder (8) according to one out of a plurality of possible channel codes. The output symbols of the channel encoder (8) are applied to transmit means (10). These output symbols are modulated on a carrier and applied to an antenna (12). An antenna (14) connected to a receiver (16) receives the signal transmitted by the antenna (12). Receive means (18) are arranged for amplifying and demodulating the signal received from the antenna (14). The output of the receive means (18) are applied to quantizing means (20) which convert its input signal into a quantized digital signal, before applying it to a Viterbi decoder 22. The complexity of the Viterbi decoder 22 depends on the number of quantization levels at the output of the quantization means (20).