Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A process manufacturing method, a method for adjusting a threshold voltage, a device, and a storage medium are provided.

Abstract: The method includes providing a to-be-etched layer including an first region and a second region adjoining the first region, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of the first region, forming a sidewall spacer on the core layer and the first mask layer, forming a first sacrificial layer on the sidewall spacer on the surface of the first mask layer of the second region, forming a second sacrificial layer on the sidewall spacer, removing the first sacrificial layer, the sidewall spacer on the surface of the first mask layer of the second region, and the sidewall spacer on a top of the core layer, removing the core layer, etching the first mask layer of the first region to form a first trench, and etching the first mask layer of the second region to form a second trench.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.

Abstract: A semiconductor structure and a forming method of a semiconductor structure are provided.

Abstract: A semiconductor structure and a forming method thereof are provided. In one form, a semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, where the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, where on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A semiconductor structure and a forming method thereof are provided. In one form, a semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, where the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, where on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.

Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor structure includes a substrate including a first region; a first polarization layer on the first region; and a first gate structure on the first polarization layer. A material of the first polarization layer includes a semiconductor compound material containing first polarization atoms.

Abstract: A semiconductor structure and a forming method of a semiconductor structure are provided.

Abstract: A semiconductor structure and a forming method thereof are provided, and the forming method includes: providing a base; forming, on the base, a plurality of conductive function layers extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer located on the base between the conductive function layers, and a blocking structure located in the conductive function layer, the blocking structure segmenting the conductive function layers located on two sides of the blocking structure in the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive function layers, and the blocking structure; etching the top dielectric layer located above a junction of the blocking structure and the conductive function layer and a part of the blocking structure located at a side wall of the conductive function layer, to form a via running through the top dielectric layer and exposing a part of a top and a part of a side wall of the conductive fu

Abstract: A process manufacturing method, a method for adjusting a threshold voltage, a device, and a storage medium are provided.

Abstract: The method includes providing a to-be-etched layer including an first region and a second region adjoining the first region, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of the first region, forming a sidewall spacer on the core layer and the first mask layer, forming a first sacrificial layer on the sidewall spacer on the surface of the first mask layer of the second region, forming a second sacrificial layer on the sidewall spacer, removing the first sacrificial layer, the sidewall spacer on the surface of the first mask layer of the second region, and the sidewall spacer on a top of the core layer, removing the core layer, etching the first mask layer of the first region to form a first trench, and etching the first mask layer of the second region to form a second trench.

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.

Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.

Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.