Patents by Inventor Abusaleh Jabir

Abusaleh Jabir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240053288
    Abstract: A sensor comprises a group of four memristors arranged in an array. Two of the memristors are connected in series as a first pair, and the other two memristors are connected in series as a second pair. The first and second pairs are connected in parallel between two connection points. Each memristor acts as a sensor element because it has an electrical resistance characteristic that is related to exposure to a species to be sensed. In the sensor, the resistance characteristic of the array between the first and second connection points is related to exposure to the species to be sensed. A sensor comprising a larger array can be composed of multiple groups of four memristors.
    Type: Application
    Filed: October 2, 2020
    Publication date: February 15, 2024
    Inventors: Abusaleh Jabir, Saurabh Khandelwal, Xiaohan Yang
  • Patent number: 11646749
    Abstract: A memristor-based circuit includes a voltage generator that applies a series of voltage pulses to a memristor to progressively change the resistance of the memristor. A comparator: receives an input electrical value; receives an electrical value based on the resistance of the memristor; compares the received values; and, based on the comparison, enables the application of the voltage pulses to the memristor by the voltage generator until a defined condition is satisfied. This circuit can be used to enable the memristor to be programmed to a desired resistance value, such as for use as a non-volatile memory. It can also enable the resistance of one memristor to be replicated to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or analog-to-digital converter. Other variants of the circuit enable construction of a decoder or digital-to-analog converter, and an authentication circuit.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 9, 2023
    Assignee: OXFORD BROOKES UNIVERSITY
    Inventors: Abusaleh Jabir, Saurabh Khandelwal, Xiaohan Yang
  • Publication number: 20220329254
    Abstract: A memristor-based circuit includes a voltage generator that applies a series of voltage pulses to a memristor to progressively change the resistance of the memristor. A comparator: receives an input electrical value; receives an electrical value based on the resistance of the memristor; compares the received values; and, based on the comparison, enables the application of the voltage pulses to the memristor by the voltage generator until a defined condition is satisfied. This circuit can be used to enable the memristor to be programmed to a desired resistance value, such as for use as a non-volatile memory. It can also enable the resistance of one memristor to be replicated to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or analog-to-digital converter. Other variants of the circuit enable construction of a decoder or digital-to-analog converter, and an authentication circuit.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 13, 2022
    Inventors: Abusaleh Jabir, Saurabh Khandelwal, Xiaohan Yang
  • Patent number: 10996182
    Abstract: A sensor comprises a plurality of sensor elements arranged in an array. Each sensor element is memristive and has an electrical resistance characteristic related to exposure to a species to be sensed. The sensor elements are arranged to be connectable such that at least one sensor element is connected in parallel with at least one other sensor element. By using appropriate connections, the array of sensor elements can be read.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 4, 2021
    Assignee: OXFORD BROOKES UNIVERSITY
    Inventors: Abusaleh Jabir, Marco Ottavi, Jimson Mathew, Eugenio Martinelli, Corrado Di Natale, Adedotun Adeyemo
  • Publication number: 20190227017
    Abstract: A sensor comprises a plurality of sensor elements arranged in an array. Each sensor element is memristive and has an electrical resistance characteristic related to exposure to a species to be sensed. The sensor elements are arranged to be connectable such that at least one sensor element is connected in parallel with at least one other sensor element. By using appropriate connections, the array of sensor elements can be read.
    Type: Application
    Filed: October 4, 2017
    Publication date: July 25, 2019
    Inventors: Abusaleh Jabir, Marco Ottavi, Jimson Mathew, Eugenio Martinelli, Corrado Di Natale, Adedotun Adeyemo
  • Patent number: 9645886
    Abstract: Error-correcting circuit includes: component generating a first output from first and second inputs; error detector generating an error flag indicative of whether or not an error is detected in the first output, based on the first output, and the first and second inputs; correction generator generating a correcting output after a first time period beginning with a timing event, based on the first output, and the first and second inputs; and output generator generating an output after a second time period beginning with the timing event. If the error flag indicates a detected error then the second time period may be longer than the first time period, otherwise it may be not longer, and the error-correcting circuit output may include a combination of the first output and the correcting output whereby the detected error is corrected, otherwise the error-correcting circuit output may correspond directly to the first output.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: May 9, 2017
    Assignee: Oxford Brookes University
    Inventors: Mahesh Poolakkaparambil, Abusaleh Jabir, Jimson Mathew, Dhiraj K. Pradhan
  • Publication number: 20140229786
    Abstract: An error-correcting circuit comprises: a component arranged to generate a first output from a first input and a second input; an error detector arranged to generate an error flag indicative of whether or not it has detected an error in the first output, based on the first output, the first input and the second input; a correction generator suitable for generating a correcting output after a first time period beginning with a timing event, based on the first output, the first input and the second input; and an output generator arranged to generate an output of the error-correcting circuit after a second time period beginning with the timing event. If the error flag indicates that an error has been detected in the first output then the second time period may be longer than the first time period, otherwise the second time period may be not longer than the first time period.
    Type: Application
    Filed: August 10, 2012
    Publication date: August 14, 2014
    Applicant: OXFORD BROOKES UNIVERSITY
    Inventors: Mahesh Poolakkaparambil, Abusaleh Jabir, Jimson Mathew, Dhiraj K. Pradhan