Abstract: In an embodiment, an integrated circuit includes a communication interface configured to be coupled to a communication bus and an input circuit. The communication interface has a plurality of terminals. The input circuit has a first input coupled to a first terminal of the plurality of terminals, and a second input coupled to a second terminal of the plurality of terminals. The first input of the input circuit is configured to receive a first signal and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first and second signals while the communication interface is unselected.

Abstract: In accordance with some embodiments, a method is provided. The method includes accessing a predefined numeric sequence at an application processor. The method further includes receiving, from a sensor of the sensor system, a verification sequence having a predetermined quantity of repetitions of the predefined numeric sequence. The method further includes correlating the verification sequence with the predefined numeric sequence. The method further includes counting a quantity of correlations between the predefined numeric sequence and the verification sequence. The method further includes adjusting a parameter of the sensor or the application processor in response to the predetermined quantity of repetitions not equaling the quantity of correlations.

Abstract: In an embodiment, an integrated circuit includes a communication interface configured to be coupled to a communication bus and an input circuit. The communication interface has a plurality of terminals. The input circuit has a first input coupled to a first terminal of the plurality of terminals, and a second input coupled to a second terminal of the plurality of terminals. The first input of the input circuit is configured to receive a first signal and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first and second signals while the communication interface is unselected.

Abstract: In accordance with some embodiments, a method is provided. The method includes accessing a predefined numeric sequence at an application processor. The method further includes receiving, from a sensor of the sensor system, a verification sequence having a predetermined quantity of repetitions of the predefined numeric sequence. The method further includes correlating the verification sequence with the predefined numeric sequence. The method further includes counting a quantity of correlations between the predefined numeric sequence and the verification sequence. The method further includes adjusting a parameter of the sensor or the application processor in response to the predetermined quantity of repetitions not equaling the quantity of correlations.

Abstract: In accordance with some embodiments, a method is provided. The method includes accessing a predefined numeric sequence at an application processor. The method further includes receiving, from a sensor of the sensor system, a verification sequence having a predetermined quantity of repetitions of the predefined numeric sequence. The method further includes correlating the verification sequence with the predefined numeric sequence. The method further includes counting a quantity of correlations between the predefined numeric sequence and the verification sequence. The method further includes adjusting a parameter of the sensor or the application processor in response to the predetermined quantity of repetitions not equaling the quantity of correlations.

Abstract: In accordance with some embodiments, a method is provided. The method includes accessing a predefined numeric sequence at an application processor. The method further includes receiving, from a sensor of the sensor system, a verification sequence having a predetermined quantity of repetitions of the predefined numeric sequence. The method further includes correlating the verification sequence with the predefined numeric sequence. The method further includes counting a quantity of correlations between the predefined numeric sequence and the verification sequence. The method further includes adjusting a parameter of the sensor or the application processor in response to the predetermined quantity of repetitions not equaling the quantity of correlations.

Abstract: A method for generating Manchester-decoded binary values is disclosed, in which a signal having signal edges is first of all read in. A first sequence of decoded binary values is then generated by means of first Manchester decoding, in which a decoded binary value is allocated to each signal edge of the signal. A second sequence of decoded binary values is then generated by means of second Manchester decoding, in which a decoded binary value is allocated to every second signal edge. The second sequence is rejected if a signal edge of the signal which is not allowed with respect to the second Manchester decoding occurs. The first sequence is rejected if a signal edge of the signal which is required with respect to the first Manchester decoding is missing.

Abstract: A method for generating Manchester-decoded binary values is disclosed, in which a signal having signal edges is first of all read in. A first sequence of decoded binary values is then generated by means of first Manchester decoding, in which a decoded binary value is allocated to each signal edge of the signal. A second sequence of decoded binary values is then generated by means of second Manchester decoding, in which a decoded binary value is allocated to every second signal edge. The second sequence is rejected if a signal edge of the signal which is not allowed with respect to the second Manchester decoding occurs. The first sequence is rejected if a signal edge of the signal which is required with respect to the first Manchester decoding is missing.

Abstract: The clock signal generator can be used to generate a first and/or a second output clock signal from an input clock signal. The rising and/or falling edges of the input clock signal are shifted using delay stages. The clock signal generator has a delay stage with a plurality of delay elements that are wired up in parallel and that have different delay lengths, and a selection device that is used to determine which of the output signals from the delay elements is to be output as the output signal of the delay stage.

Abstract: A circuit configuration includes a plurality of identical circuit blocks, at least one input terminal, at least one output terminal, a comparison device and a controlled switching device. The controlled switching device is to be connected to the identical circuit blocks, to the comparison device, to the at least one input terminal and to the at least one output terminal for coupling the identical circuit blocks to each other. The controlled switching device couples the at least one input terminal to the input side of the identical circuit blocks for supplying a path for input test patterns from the at least one input terminal to the identical circuit blocks. The controlled switching device couples the output side of the identical circuit blocks to the comparison device for supplying a path for output test patterns from each of the identical circuit blocks to the comparison device.