Abstract: A method of adjusting equalization parameters in a receiver wherein a bit error rate (BER) in a data stream is measured from the number of corrected bits in data blocks which have an information section and an error correction section. A predetermined equalization parameter is changed, and the bit error rate (BER) after change is again measured to find out how to change the predetermined equalization parameter until an optimum is reached. When adjusting the threshold value of the receiver, the history of occurring bits preceding the actual sampled bit is taken into consideration in that the amount and direction of adjustment is derived from a look-up table.

Abstract: A method of adjusting equalization parameters in a receiver wherein a bit error rate (BER) in a data stream is measured from the number of corrected bits in data blocks which have an information section and an error correction section. A predetermined equalization parameter is changed, and the bit error rate (BER) after change is again measured to find out how to change the predetermined equalization parameter until an optimum is reached. When adjusting the threshold value of the receiver, the history of occurring bits preceding the actual sampled bit is taken into consideration in that the amount and direction of adjustment is derived from a look-up table.

Abstract: A demultiplexer for an isochronous multiplex signal is described which signal consists of isochronous sub-signals interleaved block by block. The demultiplexer comprises a read-write memory (MXA, MXB, MXC, MXD) as well as a read-write control (ST). The proposed circuit arrangement may be devised in a highly advantageous manner as an integrated circuit because it is has been considered that, for example, the manufacturers of gate arrays leave the user only the choice of using building blocks depicted in a catalogue. These building blocks constitute the function blocks (MXA to MXD) which are provided for partitioning an STM-16 signal into four sub-signals (STM4A, STM4B, STM4C, STM4D). The control signals for these function blocks (TL15:0, Z(3:0), T311, T622) are produced by a control circuit (ST) whose central module is a four-stage cyclic counter. The necessary control signals are derived from the count of the cyclic counter by means of addressable demultiplexers.

Abstract: A synchronizing pulse is produced upon detection of a frame codeword or frame-structured binary signal consisting of a first word repeated a plurality of times and at least one second word. A demultiplexer divides the incoming signal into n words which are advanced in parallel through n shift registers of a first memory matrix, followed by the next n words, and so on. A decoder determines whether the first word is stored in each register, and increments a respective one of n counters when the word is found. An addressing logic transforms the output into a binary number which controls a multiplexer which, in turn controls arrangement of bits in a second memory matrix. A synchronizing pulse is produced when the second memory matrix contains predetermined bits of the first and second word.

Abstract: The described demultiplexer is intended for a serial and isochronous multiplex signal consisting of Q isochronous tributary signals interleaved bock-by-block, each block containing K bits. An associated multiplexer is also described. In order to keep the required memory capacity in a demultiplexer as small as possible, a write/read memory (5) is utilized, into which the bits of the multiplex signal are cyclically written and from which, simultaneously, the bits of the tributary signals are read out cyclically. A write/read control (4) coordinates the writing and reading processes in a manner such that no collisions occur. In an exemplary embodiment the bits of the multiplex signal are written into the write/read memory (5) bit-by-bit by means of a serial-to-parallel converter (2). Reading is effected bit-by-bit while utilizing read logics (81, 82, 83, 84) which are also controlled by the write/read control (4) via addresses.