Abstract: In a circuit arrangement for steepening signal slopes of a digital signal in the form of a sequence of amplitude-discrete sampling values of an analog signal, the digital signal to be steepened is applied to a slope detector (1) which supplies a marking signal during the period in which a slope of the digital signal exceeds a given steepness value, which marking signal marks the sequence including the slope of the digital signal to be steepened, while a delay circuit (5) is provided in which the digital signal and the marking signal are delayed by a fixed period of time whose duration is longer than the maximum period of the sequences to be steepened, and a FIFO memory (6) is provided into which the amplitude value of the digital signal is entered at the instant of the end of the non-delayed sequence and from which memory the value is read at the instant of the start of the delayed sequence, and a sequence generator (8, 22) is provided which generates a steepened signal while taking account of the delayed dig