Abstract: Systems and methods of dynamic host code generation from architecture description for fast simulation. In accordance with a method embodiment of the present invention, a method of simulating execution of a first plurality of processor instructions written in a first instruction set comprises generating a second plurality of processor instructions in a second instruction set for emulating the first plurality of processor instructions. The generating is based upon the high level description of the instruction set and/or simulated state information during the simulating.

Abstract: Generating an instruction set for an architecture. A hierarchical description of an architecture is accessed. Groups in the hierarchical description that can be pre-encoded without increasing final width of said instruction set are pre-encoded. The hierarchical description is permutated into a plurality of variations. Each variation comprises a leaf-group and one or more sub-graphs to be encoded. For each said variation, the leaf-group and the one or more sub-graphs are encoded to produce a potential instruction set for each variation. One of the potential instruction sets is selected.

Abstract: Systems and methods of user interface for facilitation of high level generation of processor extensions. In accordance with a method embodiment of the present invention, an instruction format is accessed at a graphical user interface. A programming language description of a computation element for an execution unit of the processor extension is accessed. A representation of a hardware design for the processor extension comprising the instruction format and the computation element is generated.

Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.

Abstract: Generating an instruction set for an architecture. A hierarchical description of an architecture is accessed. Groups in the hierarchical description that can be pre-encoded without increasing final width of said instruction set are pre-encoded. The hierarchical description is permutated into a plurality of variations. Each variation comprises a leaf-group and one or more sub-graphs to be encoded. For each said variation, the leaf-group and the one or more sub-graphs are encoded to produce a potential instruction set for each variation. One of the potential instruction sets is selected.

Abstract: Generating an instruction set for an architecture. A hierarchical description of an architecture is accessed. Groups in the hierarchical description that can be pre-encoded without increasing final width of said instruction set are pre-encoded. The hierarchical description is permutated into a plurality of variations. Each variation comprises a leaf-group and one or more sub-graphs to be encoded. For each said variation, the leaf-group and the one or more sub-graphs are encoded to produce a potential instruction set for each variation. One of the potential instruction sets is selected.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.

Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.

Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.

Abstract: Translating to a hardware description language (HDL) from an architecture description language (ADL) is disclosed. An architecture description that is written in the ADL and has a hierarchical organization is received. Decoders are generated, described in the HDL, from the architecture description written in the ADL. Control signals are generated, described in the HDL, from the architecture description written in the ADL. The decoders are configured to output the control signals and the control signals are input to functional units in order to preserve the hierarchical organization of the architecture description written in the ADL.

Abstract: Generating a simulator from an architecture description. A target architecture model described in an architecture description language (ADL) is accessed. The model comprises a semantic representation of an instruction set for the target architecture. The semantic representation is translated to a behavioral representation. The simulator is automatically generated from the behavioral representation. A compiler may also be generated from the semantic representation.

Abstract: Systems and methods of dynamic host code generation from architecture description for fast simulation. In accordance with a method embodiment of the present invention, a method of simulating execution of a first plurality of processor instructions written in a first instruction set comprises generating a second plurality of processor instructions in a second instruction set for emulating the first plurality of processor instructions. The generating is based upon the high level description of the instruction set and/or simulated state information during the simulating.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.