Abstract: A sensor arrangement for detection of proximity and/or touching including least one sensor supporting surface having a first flat face and a second flat face, a proximity and/or touching sensor which is connected to the first flat face and/or to the second flat face of the sensor supporting surface, a decoration supporting medium with a first support flat face and a second support flat face, a decoration layer which is connected to the first support flat face and/or to the second support flat face of the decoration supporting medium, and/or is an integral component of the decoration supporting medium. In this case, the sensor supporting surface and the decoration supporting medium are connected to one another such that a connection along their mutually facing flat face and support flat face is not formed, or is partially formed.

Abstract: A sensor assembly and method for producing a sensor assembly for detecting an approaching and/or contacting object. The sensor assembly includes at least one sensor support surface having a first flat side and a second flat side, a proximity and/or contact sensor, which is connected to the first flat side and/or to the second flat side of the sensor support surface, a decoration support medium having a first support flat side and a second support flat side, and a decoration layer, which is connected to the first support flat side and/or to the second support flat side of the decoration support medium and/or is an integral part of the decoration support medium. The decoration support medium includes a glass or plastic film or panel which is back-molded on the first support flat side thereof and/or on the second support flat side, directly or indirectly, using an injection molding material.

Abstract: A sensor assembly and method for producing a sensor assembly for detecting an approaching and/or contacting object. The sensor assembly includes at least one sensor support surface having a first flat side and a second flat side, a proximity and/or contact sensor, which is connected to the first flat side and/or to the second flat side of the sensor support surface, a decoration support medium having a first support flat side and a second support flat side, and a decoration layer, which is connected to the first support flat side and/or to the second support flat side of the decoration support medium and/or is an integral part of the decoration support medium. The decoration support medium includes a glass or plastic film or panel which is back-molded on the first support flat side thereof and/or on the second support flat side, directly or indirectly, using an injection molding material.

Abstract: A sensor arrangement for detection of proximity and/or touching including least one sensor supporting surface having a first flat face and a second flat face, a proximity and/or touching sensor which is connected to the first flat face and/or to the second flat face of the sensor supporting surface, a decoration supporting medium with a first support flat face and a second support flat face, a decoration layer which is connected to the first support flat face and/or to the second support flat face of the decoration supporting medium, and/or is an integral component of the decoration supporting medium. In this case, the sensor supporting surface and the decoration supporting medium are connected to one another such that a connection along their mutually facing flat face and support flat face is not formed, or is partially formed.

Abstract: A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of inserting several floating structures, namely fill structures, in a layout wiring plane, configuring the structures into structural regions, taking the regions into consideration with respect to the wiring capacities in the vicinity of these structures for a low computational outlay, and, for each structural region (3), defining a boundary polynomial that is modeled according to the outer margins of the structural region. In the calculation of the capacity coefficient, a structural region can be taken into consideration as a whole by a large filler polygon.

Abstract: With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in the layout, the capacitance with respect to other interconnection networks contained in the layout is calculated as follows: A filter polygon is determined, which corresponds to the form of the selected interconnection network, the dimensions of the filter polygon are enlarged by a predeterminable extent relative to the dimensions of the selected interconnection networks. The portions of the other interconnection networks which overlap the filter polygon are determined, and the capacitance between the selected interconnection networks and the portions of the other interconnection networks which overlap the filter polygon is determined.

Abstract: A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of inserting several floating structures, namely fill structures, in a layout wiring plane, configuring the structures into structural regions, taking the regions into consideration with respect to the wiring capacities in the vicinity of these structures for a low computational outlay, and, for each structural region (3), defining a boundary polynomial that is modeled according to the outer margins of the structural region. In the calculation of the capacity coefficient, a structural region can be taken into consideration as a whole by a large filler polygon.

Abstract: With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in the layout, the capacitance with respect to other interconnection networks contained in the layout is calculated as follows: A filter polygon is determined, which corresponds to the form of the selected interconnection network, the dimensions of the filter polygon are enlarged by a predeterminable extent relative to the dimensions of the selected interconnection networks. The portions of the other interconnection networks which overlap the filter polygon are determined, and the capacitance between the selected interconnection networks and the portions of the other interconnection networks which overlap the filter polygon is determined.