Abstract: A graphics controller having the capacity for translating X and Y logical addresses of words in a bit map into corresponding physical row and column addresses of words in a plurality of memory chips, for addressing selected bits within a word and for refreshing a video monitor with and without window segments beginning and ending with bits located inside word boundaries.

Abstract: A coprocessor architecture specifically adapted for parallel operation as one of an array of coprocessors is described. Each of the coprocessors of the array are commonly responsive to a host processor. The coprocessor architecture preferably includes a selector for enabling the responsiveness of the coprocessor architecture to instructions from the host processor including an enabled responsiveness unique among the plurality of coprocessors and enabled responsiveness that is in common with that of the plurality of the coprocessors. The coprocessor architecture further includes a microengine for qualifying the responsiveness of the coprocessor to instructions provided by the host processor including qualification of the enabled responsiveness of the coprocessor architecture as provided for by the selector.