Abstract: A watchdog circuit for monitoring a plurality of processes. The watchdog circuit is configured to provide a periodic signal with an adjustable fixed time interval to a control circuit. The control circuit is configured to receive the periodic signal from the timer and use periodic signal to monitor the plurality of processes. Each of the plurality of processes has a planned process duration. The fixed time interval is set to be longer than the longest planned process duration of the plurality of planned process durations.

Abstract: According to an embodiment, a receiver is described comprising an input configured to receive a digital input signal and a digital filter configured to deliver a filtered digital output signal and to deliver stability information wherein the digital filter is configured to enter or stay in a transition state after a transition at the input signal, leave the transition state when the input signal is considered being stable, update the output signal when leaving the transition state and deliver the stability information indicating transitions at the input signal during transition state.

Abstract: According to an embodiment, a receiver is described comprising an input configured to receive a digital input signal and a digital filter configured to deliver a filtered digital output signal and to deliver stability information wherein the digital filter is configured to enter or stay in a transition state after a transition at the input signal, leave the transition state when the input signal is considered being stable, update the output signal when leaving the transition state and deliver the stability information indicating transitions at the input signal during transition state.

Abstract: A method is described, for use in a data processing system, the system having a node and a communication link, wherein the communication link is coupled to the node. The method can comprise obtaining first digital signal information associated with a first signal, transmitting the first signal from the node to the communication link, receiving a second signal from the communication link at the node, and analyzing the second signal to obtain second digital signal information. The method can further include combining first digital signal information with second digital signal information and flagging a combination outside a predetermined condition space. Further, an apparatus, for use in the data processing system is described that can be operative to perform the method. A data processing system is also described.

Abstract: A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time.

Abstract: A method is described, for use in a data processing system, the system having a node and a communication link, wherein the communication link is coupled to the node. The method can comprise obtaining first digital signal information associated with a first signal, transmitting the first signal from the node to the communication link, receiving a second signal from the communication link at the node, and analysing the second signal to obtain second digital signal information. The method can further include combining first digital signal information with second digital signal information and flagging a combination outside a predetermined condition space. Further, an apparatus, for use in the data processing system is described that can be operative to perform the method. A data processing system is also described.

Abstract: A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time.

Abstract: A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage (i.e., memories or memory areas) in which data to be transmitted or received is temporarily stored, and a control device that determines whether or not any data is to be transmitted and, if appropriate, in which storage the data that are to be transmitted next is stored and/or in which storage the received data is to be stored. Information not contained in the data transmitted through the bus is stored in each storage, and is used to allocate a priority level to the respective storage, and the control device takes this information into account to decide the storage in which the next data to be transmitted will be stored and/or the storage in which the received data is to be stored.

Abstract: A bus interface connects a device to a bus that connects a plurality of devices to one another. The bus interface described is distinguished in that a timer provided in the bus interface or a timer provided in the chip that contains the bus interface is used to ascertain the timing of operations taking place within the bus interface and/or on the bus. This allows data required for configuring the bus interface to be acquired more simply, more quickly, more accurately and more comprehensively than is the case up to now. In addition, the bus interface is consequently able to match itself to the given circumstances.

Abstract: A CAN module contains several sets of storage elements for storing several sets of data representing different states of components of the CAN module. For example, a single bit stream processor component, one of the largest and most complicated constituents of the CAN module, can be used for a plurality of CAN buses when data representations of the different states of the bit stream processor are stored in the sets of storage elements. The CAN module can be used as a shared CAN module for several CAN buses and/or CAN nodes.

Abstract: A bus system has a bus, a number of units which can be connected to one another via the bus, and a bus controller. The units request the bus controller for bus access when they require a connection to one or more other units, and the bus controller decides which unit will be allocated to the bus. The bus system is distinguished in that at least some of the units which can request bus access are allocated values which indicate how long and/or how frequently the relevant unit can be allocated the bus or has been allocated the bus, and in that these values are used to decide whether a unit which is requesting bus access is allocated the bus, or whether a unit which requires bus access is requesting the bus at all.

Abstract: A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage (i.e., memories or memory areas) in which data to be transmitted or received is temporarily stored, and a control device that determines whether or not any data is to be transmitted and, if appropriate, in which storage the data that are to be transmitted next is stored and/or in which storage the received data is to be stored. Information not contained in the data transmitted through the bus is stored in each storage, and is used to allocate a priority level to the respective storage, and the control device takes this information into account to decide the storage in which the next data to be transmitted will be stored and/or the storage in which the received data is to be stored.

Abstract: A bus interface connects a device to a bus that connects a plurality of devices to one another. The bus interface described is distinguished in that a timer provided in the bus interface or a timer provided in the chip that contains the bus interface is used to ascertain the timing of operations taking place within the bus interface and/or on the bus. This allows data required for configuring the bus interface to be acquired more simply, more quickly, more accurately and more comprehensively than is the case up to now. In addition, the bus interface is consequently able to match itself to the given circumstances.

Abstract: A bus system has a bus, a number of units which can be connected to one another via the bus, and a bus controller. The units request the bus controller for bus access when they require a connection to one or more other units, and the bus controller decides which unit will be allocated to the bus. The bus system is distinguished in that at least some of the units which can request bus access are allocated values which indicate how long and/or how frequently the relevant unit can be allocated the bus or has been allocated the bus, and in that these values are used to decide whether a unit which is requesting bus access is allocated the bus, or whether a unit which requires bus access is requesting the bus at all.

Abstract: A CAN module is characterized in that it contains several sets of storage elements for storing several sets of data representing different states of the CAN module. In this way, the CAN module can be used as a shared CAN module for several CAN buses/nodes with only a minimal expenditure required.

Abstract: The lock detector circuit for a phase-locked loop has two counters and a comparator, to which the counter readings of the two counters are fed. The lock detector circuit is symmetric and has two comparators in which the counter readings of the counters are checked separately in each case. If the difference between the counter readings exceeds a predetermined threshold value in one of the comparators, then the phase-locked loop is immediately set to the non-locked state and the counter readings are reset to zero. Frequency differences are detected immediately in the novel lock detector circuit, without a time delay and independently of the relative position of the reference edges of the signals to be compared. The phase-locked loop is thus quickly and reliably set to a locked or non-locked state. Furthermore, the functioning of the lock detector circuit is preserved when one of the two clock signals fails to appear, for example in the event of a crystal fault.

Abstract: The bridge module is connected between at least two bus systems and is suitable for serial data transfer of binary data from one of the bus systems to the other one of the bus systems. A single memory device is provided for buffer storage of the data during a data transfer. The data transfer, which is controlled exclusively by the data to be transmitted, is thus carried out in a simple manner and completely automatically, without the interposition of a processor unit. It is thereby possible very easily and thus also at an attractive cost to specify a module which is suitable for the data transfer between different bus systems.