Abstract: A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and scan data into a storage element contained in the memory cell. The use of separate clock signals permits transmission of scan data and functional data via separate paths, thereby eliminating additional circuitry that are otherwise needed to multiplex such scan and functional data through a same path. The absence of such additional circuitry reduces the time delays from input to output. The structure of the memory cell provided also permits easy addition of logic functions without substantially affecting operating speeds.

Abstract: A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and scan data into a storage element contained in the memory cell. The use of separate clock signals permits transmission of scan data and functional data via separate paths, thereby eliminating additional circuitry that are otherwise needed to multiplex such scan and functional data through a same path. The absence of such additional circuitry reduces the time delays from input to output. The structure of the memory cell provided also permits easy addition of logic functions without substantially affecting operating speeds.