Patents by Inventor Achmed Rumi Zahir
Achmed Rumi Zahir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9690353Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.Type: GrantFiled: March 13, 2013Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Douglas Moran, Achmed Rumi Zahir, William Knolla, Hartej Singh, Vasudev Vasu Bibikar, Sanjeev Jahagirdar, Michael Klinglesmith, Irwin Vaz, Varghese George
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Patent number: 8843727Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.Type: GrantFiled: September 30, 2004Date of Patent: September 23, 2014Assignee: Intel CorporationInventors: Ioannis Schoinas, Gilbert Neiger, Rajesh Madukkarumukumana, Ku-jei King, Richard Uhlig, Achmed Rumi Zahir, Koichi Yamada
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Publication number: 20140281616Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Inventors: Douglas Moran, Achmed Rumi Zahir, William Knolla, Hartej Singh, Vasudev Vasu Bibikar, Sanjeev Jahagirdar, Michael Klinglesmith, Irwin Vaz, Varghese George
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Patent number: 7680990Abstract: Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.Type: GrantFiled: May 30, 2003Date of Patent: March 16, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Donald C. Soltis, Dale C. Morris, Dean Ahmad Mulla, Achmed Rumi Zahir, Amy Lynn O'Donnell, Allan Douglas Knies
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Publication number: 20100011187Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.Type: ApplicationFiled: September 1, 2009Publication date: January 14, 2010Inventors: Ioannis Schoinas, Gilbert Neiger, Rajesh Madukkarumukumana, Ku-Jei King, Richard Uhlig, Achmed Rumi Zahir, Koichi Yamada
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Patent number: 7334112Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: GrantFiled: November 6, 2003Date of Patent: February 19, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
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Patent number: 7325228Abstract: A method of converting an original code sequence to a modified code sequence where the original code sequence includes a procedure call that is prior to a load instruction to one of a first plurality of registers is provided. The method includes inserting the load instruction into the modified code sequence and inserting the procedure call into the modified code sequence subsequent to the load instruction. The method further includes inserting an advanced load instruction to one of a second plurality of registers into the modified code sequence prior to the procedure call and inserting a checking instruction associated with the advanced load instruction into the modified code sequence subsequent to the procedure call.Type: GrantFiled: April 30, 2003Date of Patent: January 29, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Dale C. Morris, Jonathan Ross, Achmed Rumi Zahir
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Patent number: 7272702Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: GrantFiled: November 6, 2003Date of Patent: September 18, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
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Publication number: 20040243790Abstract: Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.Type: ApplicationFiled: May 30, 2003Publication date: December 2, 2004Inventors: Donald C. Soltis, Dale C. Morris, Dean Ahmad Mulla, Achmed Rumi Zahir, Amy Lynn Santoni, Allan Douglas Knies
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Patent number: 6766419Abstract: Program instructions permit software management of a processor cache. The program instructions may permit a software designer to provide software deallocation hints identifying data that is not likely to be used during further program execution. The program instructions may permit a processor to evict the identified data from a cache ahead of other eviction candidates that are likely to be used during further program execution. Thus, these software hints provide for better use of cache memory.Type: GrantFiled: March 31, 2000Date of Patent: July 20, 2004Assignee: Intel CorporationInventors: Achmed Rumi Zahir, Jeffrey Baxter
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Publication number: 20040123081Abstract: A mechanism for increasing the performance of control speculation comprises executing a speculative load, returning a data value to a register targeted by the speculative load if it hits in a cache, and associating a deferral token with the speculative load if it misses in the cache. The mechanism may also issue a prefetch on a cache miss to speed execution of recovery code if the speculative load is subsequently determined to be on the control flow path.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Allan Knies, Kevin Rudd, Achmed Rumi Zahir, Dale Morris, Jonathan K. Ross
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Publication number: 20040123083Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: ApplicationFiled: November 6, 2003Publication date: June 24, 2004Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
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Publication number: 20040093486Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: ApplicationFiled: November 6, 2003Publication date: May 13, 2004Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
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Patent number: 6708256Abstract: A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location.Type: GrantFiled: August 29, 2002Date of Patent: March 16, 2004Assignee: Intel CorporationInventor: Achmed Rumi Zahir
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Patent number: 6665793Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.Type: GrantFiled: December 28, 1999Date of Patent: December 16, 2003Assignee: Institute for the Development of Emerging Architectures, L.L.C.Inventors: Achmed Rumi Zahir, Cary A. Coutant, Carol L. Thompson, Jonathan K. Ross
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Patent number: 6665783Abstract: A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location.Type: GrantFiled: March 6, 2003Date of Patent: December 16, 2003Assignee: Intel CorporationInventor: Achmed Rumi Zahir
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Publication number: 20030182515Abstract: A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location.Type: ApplicationFiled: March 6, 2003Publication date: September 25, 2003Inventor: Achmed Rumi Zahir
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Publication number: 20030009636Abstract: A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location.Type: ApplicationFiled: August 29, 2002Publication date: January 9, 2003Inventor: Achmed Rumi Zahir
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Patent number: 6502170Abstract: A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location.Type: GrantFiled: December 15, 2000Date of Patent: December 31, 2002Assignee: Intel CorporationInventor: Achmed Rumi Zahir
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Publication number: 20020078307Abstract: A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location.Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Inventor: Achmed Rumi Zahir