Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.

Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.

Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.

Abstract: An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold.

Abstract: An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.

Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.

Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.

Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.

Abstract: A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.

Abstract: A reconfigurable P-way parallel N-tap feed forward equalizer includes an adaptive filter configured to generate a series of coefficients (taps) and an input register for storing input symbols. A variable cursor position defined by a parameter corresponding to a position in the input register selects a set of pre-cursor and post-cursor taps for dynamic ISI correction of a like set of pre-cursor and post-cursor symbols. Multiplier banks generate partial result symbols by applying the taps to the set of input symbols, and a set of combiners or adder banks generate equalized output symbols from the partial result symbols. Two multiplexers adjust input symbols and coefficients according to the parameter, and a controller allows selection of an optimal parameter, and thus an optimal variable cursor position. The coefficient corresponding to the parameter may additionally be preset to save storage space.

Abstract: The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver based on the normalized Nyquist energy.

Abstract: An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

Abstract: An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

Abstract: The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver based on the normalized Nyquist energy.

Abstract: In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

Abstract: In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

Abstract: Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data.

Abstract: One embodiment of the present invention processes a signal of interest through an optional reference channel, combines the resulting signal with white noise, and then processes the noisy signal through a reference receiver. Two metrics are calculated from the results of that processing: Non-Compensable Data-Dependent Jitter (NC-DDJ) and Enhanced Transmitter and Waveform Dispersion Penalty (Enhanced TWDP). Within the reference receiver, a variable delay module sweeps the eye opening defined by the noise-free samples of the signal of interest and determines the transition points (i.e., edges) of the eye opening. Those transition points are compared to the Unit Interval to yield NC-DDJ. Further, the signal-to-noise ratio (SNR) of the noisy samples of the signal of interest is compared to the SNR of an ideal receiver (i.e., matched filter) driven by an ideal transmitter via an ideal channel with additive white Gaussian noise n(t) to yield Enhanced TWDP.

Abstract: Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.

Abstract: Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data.