Patents by Inventor Adam Capewell

Adam Capewell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070212879
    Abstract: A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining striped regions (16) on the surface of a silicon substrate (10) at which dislocations can preferentially form, growing a first SiGe layer (18) on the strips such that first dislocations (20) extend preferentially across the first SiGe layer between the striped regions to relieve the strain in the first SiGe layer in directions transverse to the stripes (16), and growing a second SiGe layer on top of the first SiGe layer such that second dislocations (22) form preferentially within the second SiGe layer to relieve the strain in the second SiGe layer in directions transverse to the first dislocations (20). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another.
    Type: Application
    Filed: September 21, 2005
    Publication date: September 13, 2007
    Inventors: Timothy Grasby, Adam Capewell, Evan Parker
  • Publication number: 20050245055
    Abstract: A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls (2) on the surface, selectively growing a first SiGe layer on the strips such that first dislocations (3) extend preferentially across the first SiGe layer between the walls (2) to relieve the strain in the first SiGe layer in directions transverse to the walls (2), and growing a second SiGe layer on top of the first SiGe layer to overgrow the walls (2) such that second dislocations form preferentially within the second SiGe layer above the walls (2) to relieve the strain in the second SiGe layer in directions transverse to the first dislocations (3). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another.
    Type: Application
    Filed: August 12, 2003
    Publication date: November 3, 2005
    Applicant: University of Warwick
    Inventors: Adam Capewell, Timothy Grasby, Evan Hubert Parker, Terence Whall
  • Publication number: 20050239255
    Abstract: In order to reduce dislocation pile-ups in a virtual substrate, a buffer layer 32 is provided, between an underlying Si substrate 34 and an uppermost constant composition SiGe layer 36, which comprises alternating graded SiGe layers 38 and uniform SiGe layers 40. During the deposition of each of the graded SiGe layers 38 the Ge fraction x is linearly increased from a value corresponding to the Ge composition ratio of the preceding layer to a value corresponding to the Ge composition ratio of the following layer. Furthermore the Ge fraction x is maintained constant during deposition of each uniform SiGe layer 40, so that the Ge fraction x varies in step-wise fashion through the depth of the buffer layer. After the deposition of each pair of graded and uniform SiGe layers 38 and 40, the wafer is annealed at an elevated temperature greater than the temperature at which the layers have been deposited.
    Type: Application
    Filed: May 30, 2003
    Publication date: October 27, 2005
    Applicant: University of Warwick
    Inventors: Adam Capewell, Timothy Grasby, Evan Hubert Parker, Terence Whall