Patents by Inventor Adam Collura
Adam Collura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11243774Abstract: Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.Type: GrantFiled: March 20, 2019Date of Patent: February 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Raymond Cuffney, Adam Collura, James Bonanno, Edward Malley, Anthony Saporito, Jang-Soo Lee, Michael Cadigan, Jr., Jonathan Hsieh
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Patent number: 11182165Abstract: A system includes a branch predictor and a processing circuit configured to perform a plurality of operations including storing a skip-over offset value in the branch predictor. The skip-over offset value defines a number of search addresses of the branch predictor to be skipped. The operations further include searching the branch predictor for a branch prediction. Responsive to finding the branch prediction, the searching of the branch predictor is re-indexed based on the skip-over offset value associated with the branch prediction.Type: GrantFiled: November 19, 2018Date of Patent: November 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Bonanno, Daniel Lipetz, Brian Robert Prasky, Anthony Saporito, Adam Collura, Steven J. Hnatko
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Patent number: 11163573Abstract: A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.Type: GrantFiled: February 13, 2019Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Bonanno, Varnika Atmakuri, Adam Collura, Brian Robert Prasky, Anthony Saporito, Suman Amugothu
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Patent number: 10990405Abstract: A computer system includes a branch detection module and a branch predictor module. The branch detection module determines that a first program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a first routine branch is a possible return capable branch having the first routine instruction address that is a detected as being offset. The branch predictor module determines that a second program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a second routine branch is a predicted return branch having a predicted target instruction address based on the NSIA of the second program branch and the predicted offset.Type: GrantFiled: February 19, 2019Date of Patent: April 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adam Collura, James Bonanno, Steven J. Hnatko, Brian Robert Prasky, Daniel Lipetz
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Patent number: 10977040Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.Type: GrantFiled: February 19, 2019Date of Patent: April 13, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Raymond Cuffney, Adam Collura, James Bonanno, Jang-Soo Lee, Eyal Naor, Yair Fried, Brian Robert Prasky
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Patent number: 10929142Abstract: Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.Type: GrantFiled: March 20, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory William Alexander, James Bonanno, Adam Collura, James Raymond Cuffney, Yair Fried, Jonathan Hsieh, Jang-Soo Lee, Edward Malley, Anthony Saporito, Eyal Naor
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Patent number: 10838659Abstract: Examples of techniques for controlling write requests to a memory structure having limited write ports are described herein. An aspect includes storing, in a first queue, write requests received from a first source having a first priority. Another aspect includes storing, in a second queue, write requests received from a second source having a second priority, wherein the second priority is lower than the first priority. Aspects also include identifying a selected queue from the first queue and the second queue based on a selection algorithm, which is a function of a state associated with the first queue and the second queue. Aspects further include forwarding a write request from the selected queue to a write port of the memory structure.Type: GrantFiled: February 8, 2019Date of Patent: November 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Varnika Atmakuri, Adam Collura, James Bonanno, Suman Amugothu
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Publication number: 20200301710Abstract: Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Inventors: Gregory William Alexander, James Bonanno, Adam Collura, James Raymond Cuffney, Yair Fried, Jonathan Hsieh, Jang-Soo Lee, Edward Malley, Anthony Saporito, Eyal Naor
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Publication number: 20200301711Abstract: Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Inventors: James Raymond Cuffney, Adam Collura, JAMES BONANNO, Edward Malley, Anthony Saporito, Jang-Soo Lee, Michael Cadigan, JR., Jonathan Hsieh
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Publication number: 20200264882Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.Type: ApplicationFiled: February 19, 2019Publication date: August 20, 2020Inventors: JAMES RAYMOND CUFFNEY, ADAM COLLURA, JAMES BONANNO, JANG-SOO LEE, EYAL NAOR, YAIR FRIED, BRIAN ROBERT PRASKY
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Publication number: 20200264887Abstract: A computer system includes a branch detection module and a branch predictor module. The branch detection module determines that a first program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a first routine branch is a possible return capable branch having the first routine instruction address that is a detected as being offset. The branch predictor module determines that a second program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a second routine branch is a predicted return branch having a predicted target instruction address based on the NSIA of the second program branch and the predicted offset.Type: ApplicationFiled: February 19, 2019Publication date: August 20, 2020Inventors: Adam Collura, James Bonanno, Steven J. Hnatko, Brian Robert Prasky, Daniel Lipetz
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Publication number: 20200257468Abstract: Examples of techniques for controlling write requests to a memory structure having limited write ports are described herein. An aspect includes storing, in a first queue, write requests received from a first source having a first priority. Another aspect includes storing, in a second queue, write requests received from a second source having a second priority, wherein the second priority is lower than the first priority. Aspects also include identifying a selected queue from the first queue and the second queue based on a selection algorithm, which is a function of a state associated with the first queue and the second queue. Aspects further include forwarding a write request from the selected queue to a write port of the memory structure.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Inventors: VARNIKA ATMAKURI, ADAM COLLURA, JAMES BONANNO, SUMAN AMUGOTHU
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Publication number: 20200257534Abstract: A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Inventors: James Bonanno, Varnika Atmakuri, Adam Collura, Brian Robert Prasky, Anthony Saporito, Suman Amugothu
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Publication number: 20200159537Abstract: A system includes a branch predictor and a processing circuit configured to perform a plurality of operations including storing a skip-over offset value in the branch predictor. The skip-over offset value defines a number of search addresses of the branch predictor to be skipped. The operations further include searching the branch predictor for a branch prediction. Responsive to finding the branch prediction, the searching of the branch predictor is re-indexed based on the skip-over offset value associated with the branch prediction.Type: ApplicationFiled: November 19, 2018Publication date: May 21, 2020Inventors: James Bonanno, Daniel Lipetz, Brian Robert Prasky, Anthony Saporito, Adam Collura, Steven J. Hnatko