Patents by Inventor Adam Duncan
Adam Duncan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9601214Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.Type: GrantFiled: June 6, 2016Date of Patent: March 21, 2017Assignee: The United States of America as represented by the Secretary of the NavyInventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
-
Patent number: 9601201Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus are provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.Type: GrantFiled: March 29, 2016Date of Patent: March 21, 2017Assignee: The United States of America as represented by the Secretary of the NavyInventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
-
Patent number: 9594117Abstract: Various apparatus and method s associated with a compact electronics test system having user programmable device interfaces and on-board functions adapted for use in various environments are provided. Exemplary embodiments can include a variety of apparatuses and method s to realize an advanced field programmable gate array adapted to perform functional tests on digital electronics within an exemplary 48-pin DIP footprint. One aspect of the invention can include a testing device comprised of components to produce a product that is inexpensive and consumable. A small size of an exemplary embodiment of the invention further allows for desirable shielding to be placed around a highly portable and highly programmable and adaptable testing device in order to protect it from external dangers found in harsh environments (e.g., high levels of radiation when operating in space, etc).Type: GrantFiled: November 24, 2014Date of Patent: March 14, 2017Assignee: The United States of America as represented by the Secretary of the NavyInventors: Adam Duncan, Matthew Gadlage
-
Patent number: 9536620Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.Type: GrantFiled: December 3, 2015Date of Patent: January 3, 2017Assignee: The United States of America as represented by the Secretary of the NavyInventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
-
Publication number: 20160284418Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
-
Publication number: 20160258999Abstract: A highly flexible, compact, lightweight, and portable testing system for use with radiation testing activities. The testing system is coupled to a device under test (DUT), which can be positioned in such a way that the top of the die package is exposed to the direct ion beam during radiation testing. A variety of sensors, onboard memory systems, programmable interfaces, onboard control systems, data output devices, and different types of interfaces are also provided which provide an ability to perform testing procedures while having a maximum ability to orient the DUT and perform a wide variety of testing currently unavailable.Type: ApplicationFiled: May 17, 2016Publication date: September 8, 2016Inventors: Matthew Gadlage, Adam Duncan
-
Patent number: 9431133Abstract: A highly flexible, compact, lightweight, and portable testing system for use with radiation testing activities. The testing system is coupled to a device under test (DUT), which can be positioned in such a way that the top of the die package is exposed to the direct ion beam during radiation testing. A variety of sensors, onboard memory systems, programmable interfaces, onboard control systems, data output devices, and different types of interfaces are also provided which provide an ability to perform testing procedures while having a maximum ability to orient the DUT and perform a wide variety of testing currently unavailable.Type: GrantFiled: June 3, 2013Date of Patent: August 30, 2016Assignee: The United States of America as represented by the Secretary of the NavyInventors: Matthew Gadlage, Adam Duncan
-
Patent number: 9425803Abstract: Methods and apparatuses for implementing a Physically Unclonable Function (PUF) and random number generator capabilities comprising providing a device under test comprising a plurality of bits comprising integrated circuits each including a capacitor; placing the bits in a first state with charge on selected bit capacitors; stopping bit refresh for a first predetermined time; re-enabling refresh for a second predetermined time to read and refresh charge on all bits; reading all bits and recording addresses of bits that have experienced bit flip from a first state to a second state comprising from “1” to “0” state; performing selecting a plurality of said recorded addresses to generate a PUF or cryptographic key; and performing an operation comprising a test or verification operation with said generated information PUF or key. Various hardware elements are also provided as well as machine readable instructions for implementing and controlling aspects of the invention.Type: GrantFiled: May 22, 2015Date of Patent: August 23, 2016Assignee: The United States of America as represented by the Secretary of the NavyInventors: Adam Duncan, Matthew Gadlage, Austin Roach, Matthew Kay
-
Patent number: 9417286Abstract: A system and method for image enhancement associated with scan generators is provided. For example, a source stimulates a device under test (DUT) at electrical interconnects. An internal clock of the DUT is synchronized with the scan rate of the source to reduce the noise of the output signal and enhance a resultant image. A phase adjustment is effected to further reduce the noise in the signal. The synchronization and the phase adjustment seek to ensure that the data is collected at uniform times relative to the reference signal and thereby reduce the noise introduced into the system, by such offsets. Post-scan processing increases the signal-to-noise ratio through averaging techniques. Using a pixel overlay algorithm the averaged data is transformed into a 2-D array and the image of the DUT reconstructed.Type: GrantFiled: March 13, 2014Date of Patent: August 16, 2016Assignee: The United States of America as represented by the Secretary of the NavyInventors: Douglas J Martin, Adam Duncan, Fred Barsun
-
Publication number: 20160211021Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus are provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.Type: ApplicationFiled: March 29, 2016Publication date: July 21, 2016Inventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
-
Publication number: 20160086676Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.Type: ApplicationFiled: December 3, 2015Publication date: March 24, 2016Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
-
Patent number: 9263139Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.Type: GrantFiled: September 30, 2014Date of Patent: February 16, 2016Assignee: The United States of America as represented by the Secretary of the NavyInventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
-
Publication number: 20150145548Abstract: Various apparatus and methods associated with a compact electronics test system having user programmable device interfaces and on-board functions adapted for use in various environments are provided. Exemplary embodiments can include a variety of apparatuses and methods to realize an advanced field programmable gate array adapted to perform functional tests on digital electronics within an exemplary 48-pin DIP footprint. One aspect of the invention can include a testing device comprised of components to produce a product that is inexpensive and consumable. A small size of an exemplary embodiment of the invention further allows for desirable shielding to be placed around a highly portable and highly programmable and adaptable testing device in order to protect it from external dangers found in harsh environments (e.g., high levels of radiation when operating in space, etc).Type: ApplicationFiled: November 24, 2014Publication date: May 28, 2015Inventors: Adam Duncan, Matthew Gadlage
-
Publication number: 20150144695Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.Type: ApplicationFiled: April 7, 2014Publication date: May 28, 2015Applicant: The United States of America as represented by the Secretary of the NavyInventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
-
Publication number: 20150145524Abstract: A method and system for determining short, open, and good connections using digital input and output (IO) structures in a device under test (DUT) continuity test, through the combined methods of using resistance-capacitance (RC) delay, time domain reflectometry (TDR), and forcing voltage on to a single IO pin of the DUT while measuring voltage on remaining IO pins of said DUT. In one embodiment, the combined methods are executed without the DUT in a test socket to produce a first set of test values and also with the DUT in a test socket to produce a second set of test values. The first and second sets of test values are compared to determine if one or more circuits of the DUT have a short circuit, an open circuit, or are a good (have an electrical connection that is not a short circuit or an open circuit) circuit.Type: ApplicationFiled: November 26, 2014Publication date: May 28, 2015Inventors: Adam Duncan, Matthew Gadlage
-
Publication number: 20150138887Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.Type: ApplicationFiled: September 30, 2014Publication date: May 21, 2015Inventors: Matthew Kay, James David Ingalls, Matthew Gadlage, Adam Duncan, Andrew Howard
-
Publication number: 20140331098Abstract: A system and method for image enhancement associated with scan generators is provided. For example, a source stimulates a device under test (DUT) at electrical interconnects. An internal clock of the DUT is synchronized with the scan rate of the source to reduce the noise of the output signal and enhance a resultant image. A phase adjustment is effected to further reduce the noise in the signal. The synchronization and the phase adjustment seek to ensure that the data is collected at uniform times relative to the reference signal and thereby reduce the noise introduced into the system, by such offsets. Post-scan processing increases the signal-to-noise ratio through averaging techniques. Using a pixel overlay algorithm the averaged data is transformed into a 2-D array and the image of the DUT reconstructed.Type: ApplicationFiled: March 13, 2014Publication date: November 6, 2014Applicant: United States of America as represented by the Secretary of the NavyInventors: Douglas J. Martin, Adam Duncan, Fred Barsun
-
Publication number: 20140330533Abstract: A highly flexible, compact, lightweight, and portable testing system for use with radiation testing activities. The testing system is coupled to a device under test (DUT), which can be positioned in such a way that the top of the die package is exposed to the direct ion beam during radiation testing. A variety of sensors, onboard memory systems, programmable interfaces, onboard control systems, data output devices, and different types of interfaces are also provided which provide an ability to perform testing procedures while having a maximum ability to orient the DUT and perform a wide variety of testing currently unavailable.Type: ApplicationFiled: June 3, 2013Publication date: November 6, 2014Inventors: Matthew Gadlage, Adam Duncan
-
Patent number: 8165848Abstract: A method of inspecting equipment to ensure quality control that employs a computer program to assist in the inspection. The program contains an inspection protocol adapted to specific equipment. The inspector follows the protocol to inspect component parts of the equipment. The inspection protocol can only be closed, indicating completion of the inspection, when the protocol has been followed. The program is capable of generating a variety of inspection reports.Type: GrantFiled: February 26, 2009Date of Patent: April 24, 2012Assignee: Knight Information Systems, LLCInventors: Mark Edward Knight, Mickey Paul Broussard, Adam Duncan Ashe
-
Publication number: 20100217554Abstract: A method of inspecting equipment to ensure quality control that employs a computer program to assist in the inspection. The program contains an inspection protocol adapted to specific equipment. The inspector follows the protocol to inspect component parts of the equipment. The inspection protocol can only be closed, indicating completion of the inspection, when the protocol has been followed. The program is capable of generating a variety of inspection reports.Type: ApplicationFiled: February 26, 2009Publication date: August 26, 2010Inventors: Mark Edward Knight, Mickey Paul Broussard, Adam Duncan Ashe