Patents by Inventor Adam G. Kimura

Adam G. Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250165686
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins
  • Patent number: 12229482
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: February 18, 2025
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins
  • Publication number: 20230377127
    Abstract: To validate an integrated circuit (IC), the IC is imaged by scanning an optical beam over the IC to optically inject carriers and measuring an output signal generated by the IC in response to the injected optical carriers. A comparison between the image of the IC and a reference image is computed, and suspect regions of the IC are identified based on the comparison. The reference image may be an image of a reference IC. In another approach, images of training ICs are acquired, and a deep learning algorithm is trained to transform corresponding training IC layouts to the images of the training ICs. The trained deep learning algorithm then transforms a layout of the IC to generate the reference image. The comparison may be computed by computing an error metric for each region corresponding to a standard cell in the reference image.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 23, 2023
    Inventors: Thomas F. Kent, Adam G. Kimura, Katie T. Liszewski, Anthony F. George, Jeffrey A. Simon, Brian P. Dupaix
  • Publication number: 20230298159
    Abstract: An integrated circuit (IC) layout extraction method includes executing: an image receiving pipeline that, for each tile n of N tiles of an IC, receives a tile image n of the tile n of the IC acquired using a microscope; a layout portion extraction pipeline that extracts a layout portion n from each received tile image n; and a layout portion comparison pipeline that compares each layout portion n with a corresponding portion of the reference IC layout. The image receiving pipeline, the layout portion extraction pipeline, and the layout portion comparison pipeline are parallel pipelines that are executed by the electronic processor concurrently in time. The extracted layout portions for the N tiles of the IC are combined to form the extracted layout for the IC.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 21, 2023
    Inventors: Adam R. Waite, Adam G. Kimura, James E. Schaffranek
  • Publication number: 20230289502
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins
  • Patent number: 11651126
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: May 16, 2023
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins
  • Publication number: 20210240894
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 5, 2021
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins
  • Patent number: 11010519
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: May 18, 2021
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins
  • Publication number: 20200387654
    Abstract: A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 10, 2020
    Inventors: Adam G. Kimura, Andrew S. Elliott, Daniel A. Perkins