Abstract: A semiconductor device structure and related method forming super via (SVIA) structures using a via first, trench last (VFTL) damascene processing technique. The formed SVIA connects a top metallization level structure formed in a stack of interlevel dielectric (ILD) material layers and extends through an intermediate ILD layer and a dielectric etch stop layer therebetween to connect to an underlying metallization level structure of an underlying ILD layer below the intermediate ILD layer. The VFTL processing to form the SVIA avoids a punching through of an etch stop layer provided between the intermediate ILD layer and the bottom ILD material layer after a final trench and OPL strip. The SVIA further includes a metal plug contacting the underlying metallization level structure of the underlying ILD layer and is of a material different than the material of said metallization level structure. The formed SVIA exhibits a straight via profile and chamfer.