Patents by Inventor Adam Gildea

Adam Gildea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BONDING LAYER AND PROCESS
    Publication number: 20240170444
    Abstract: A method includes providing a first bonding surface on a first substrate, the first bonding surface including a bonding layer that is thermally curable or photocurable. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by making physical contact between the first bonding surface and second bonding surface. The method further includes applying thermal energy or light to the bonding layer.
    Type: Application
    Filed: May 19, 2023
    Publication date: May 23, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Scott LEFEVRE, Adam GILDEA, Satohiko HOSHINO, Sophia MADELONE, Yuji MIMURA
  • NEXT GENERATION BONDING LAYER FOR 3D HETEROGENEOUS INTEGRATION
    Publication number: 20240071984
    Abstract: Devices and methods for forming semiconductor devices are disclosed. The semiconductor device can include a plurality of semiconductor wafers. The plurality of semiconductor wafers can have a dielectric bonding layer disposed thereupon. The dielectric bonding layers can be treated to increase a bonding energy with other semiconductor wafers. A wafer having a treatment applied to a bonding layer can be bonded to another wafer.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Kandabara Tapily, Soo Doo Chae, Satohiko Hoshino, Hojin Kim, Adam Gildea
  • WAFER BONDING METHOD USING SELECTIVE DEPOSITION AND SURFACE TREATMENT
    Publication number: 20230075263
    Abstract: A semiconductor package is disclosed. The semiconductor package includes a first substrate including a first interconnect structure and a first bonding layer adjacent the first interconnect structure. The semiconductor package includes a second substrate including a second interconnect structure and a second bonding layer adjacent the second interconnect structure. The first bonding layer and second bonding layer each include a metal oxide.
    Type: Application
    Filed: July 13, 2022
    Publication date: March 9, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Sang Cheol Han, Hojin Kim, Kandabara Tapily, Satohiko Hoshino, Adam Gildea, Gerrit Leusink