Patents by Inventor Adam Gildea
Adam Gildea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12648155Abstract: At least one aspect of the present disclosure is directed to a semiconductor device. The semiconductor device includes a first substrate including a first area and a second area; a second substrate including a third area and a fourth area; a first bonding layer comprising a first dielectric material that bonds the first area to the third area; and a second bonding layer comprising a second dielectric material that bonds the second area to the fourth area. The first dielectric material is different from the second dielectric material.Type: GrantFiled: April 28, 2023Date of Patent: June 2, 2026Assignee: Tokyo Electron LimitedInventors: Soo Doo Chae, Matthew Baron, Adam Gildea
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Patent number: 12642154Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The methods include forming a first layer on a first substrate, treating the first layer with a nitrogen-based plasma to form a first type of dangling bonds, treating the first layer with an oxygen-based plasma to transform the first type of dangling bonds into a second type of dangling bonds, and treating the first layer with water to transform the second type of dangling bonds into a third type of dangling bonds.Type: GrantFiled: September 20, 2023Date of Patent: May 26, 2026Assignee: Tokyo Electron LimitedInventors: Adam Gildea, Satohiko Hoshino
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Patent number: 12622336Abstract: A method includes providing a first bonding surface on a first substrate, the first bonding surface including a bonding layer that is thermally curable or photocurable. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by making physical contact between the first bonding surface and second bonding surface. The method further includes applying thermal energy or light to the bonding layer.Type: GrantFiled: May 19, 2023Date of Patent: May 5, 2026Assignee: Tokyo Electron LimitedInventors: Scott Lefevre, Adam Gildea, Satohiko Hoshino, Sophia Madelone, Yuji Mimura
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Patent number: 12577665Abstract: Devices and methods for forming semiconductor devices are disclosed. The semiconductor device can include a plurality of semiconductor wafers. The plurality of semiconductor wafers can have a dielectric bonding layer disposed thereupon. The dielectric bonding layers can be treated to increase a bonding energy with other semiconductor wafers. A wafer having a treatment applied to a bonding layer can be bonded to another wafer.Type: GrantFiled: August 23, 2022Date of Patent: March 17, 2026Assignee: Tokyo Electron LimitedInventors: Kandabara Tapily, Soo Doo Chae, Satohiko Hoshino, Hojin Kim, Adam Gildea
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Patent number: 12582017Abstract: A method includes providing a first substrate with a first surface including an alkyne moiety. The method includes providing a second substrate with a second surface including an azide moiety. The method further includes bonding the first substrate to the second substrate. The bonding of the first substrate to the second substrate includes making physical contact between the first surface and the second surface at an interface and chemically reacting the alkyne moiety with the azide moiety through a cycloaddition mechanism, thereby forming a triazole moiety-linked layer at the interface.Type: GrantFiled: May 19, 2023Date of Patent: March 17, 2026Assignee: Tokyo Electron LimitedInventors: Scott Lefevre, Adam Gildea, Satohiko Hoshino, Sophia Madelone, Yuji Mimura
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Publication number: 20250372462Abstract: An example method for measuring bond front propagation during bonding includes illuminating, using a first laser beam from a first horizontal optical sensor, a gap between a first wafer and a second wafer, the second wafer held by a second platen over the first wafer. The method includes propagating a bond front to eliminate the gap and forming a bonded region between the first and the second wafers. The method includes while propagating the bond front, collecting, using the first horizontal optical sensor, a first scattered laser beam, the first scattered laser beam including a portion of the first laser beam scattered from the bond front.Type: ApplicationFiled: May 30, 2024Publication date: December 4, 2025Inventors: Andrew Tuchman, Christopher Netzband, Adam Gildea, Ilseok Son
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Publication number: 20250180453Abstract: A method of testing semiconductor surface bonds includes centering a torsional shear tool with respect to a first die having a surface bond to a wafer, clamping the first die using the torsional shear tool, applying a torsional load to the first die with respect to the wafer using the torsional shear tool, and measuring a torque value associated with the torsional load.Type: ApplicationFiled: December 4, 2023Publication date: June 5, 2025Inventors: Christopher Michael Netzband, Adam Gildea, Ilseok Son
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Publication number: 20250112083Abstract: Conformal semiconductor chucks are disclosed. The semiconductor chucks can include a first portion comprising a first vacuum pad. The semiconductor chucks can include a second portion exhibiting greater compliance than either of the first portion or a third portion. The semiconductor chucks can include the third portion comprising a second vacuum pad.Type: ApplicationFiled: October 3, 2023Publication date: April 3, 2025Applicant: Tokyo Electron LimitedInventors: Christopher NETZBAND, Adam GILDEA
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Publication number: 20250096190Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The methods include forming a first layer on a first substrate, treating the first layer with a nitrogen-based plasma to form a first type of dangling bonds, treating the first layer with an oxygen-based plasma to transform the first type of dangling bonds into a second type of dangling bonds, and treating the first layer with water to transform the second type of dangling bonds into a third type of dangling bonds.Type: ApplicationFiled: September 20, 2023Publication date: March 20, 2025Applicant: Tokyo Electron LimitedInventors: Adam GILDEA, Satohiko HOSHINO
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Publication number: 20250087521Abstract: Expandable semiconductor chucks are disclosed. The semiconductor chucks can include a first portion comprising a plurality of first couplers configured to receive a corresponding plurality of actuators. The semiconductor chucks can include a second portion circumscribed about the first portion, the second portion comprising a plurality of segments. Each segment can include a wafer holder to selectively couple the respective segment to a semiconductor wafer. Each segment can include a second coupler to receive one or more of the plurality of actuators. The actuators can extend to increase a dimension between the first portion and the second portion and retract to decrease a dimension between the first portion and the second portion.Type: ApplicationFiled: September 12, 2023Publication date: March 13, 2025Applicant: Tokyo Electron LimitedInventors: Christopher NETZBAND, Adam GILDEA
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Publication number: 20240363564Abstract: At least one aspect of the present disclosure is directed to a semiconductor device. The semiconductor device includes a first substrate including a first area and a second area; a second substrate including a third area and a fourth area; a first bonding layer comprising a first dielectric material that bonds the first area to the third area; and a second bonding layer comprising a second dielectric material that bonds the second area to the fourth area. The first dielectric material is different from the second dielectric material.Type: ApplicationFiled: April 28, 2023Publication date: October 31, 2024Applicant: Tokyo Electron LimitedInventors: Soo Doo CHAE, Matthew BARON, Adam GILDEA
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Publication number: 20240234363Abstract: A method includes providing a first substrate with a first surface including an alkyne moiety. The method includes providing a second substrate with a second surface including an azide moiety. The method further includes bonding the first substrate to the second substrate. The bonding of the first substrate to the second substrate includes making physical contact between the first surface and the second surface at an interface and chemically reacting the alkyne moiety with the azide moiety through a cycloaddition mechanism, thereby forming a triazole moiety-linked layer at the interface.Type: ApplicationFiled: May 19, 2023Publication date: July 11, 2024Applicant: Tokyo Electron LimitedInventors: Scott LEFEVRE, Adam GILDEA, Satohiko HOSHINO, Sophia MADELONE, Yuji MIMURA
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Publication number: 20240170444Abstract: A method includes providing a first bonding surface on a first substrate, the first bonding surface including a bonding layer that is thermally curable or photocurable. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by making physical contact between the first bonding surface and second bonding surface. The method further includes applying thermal energy or light to the bonding layer.Type: ApplicationFiled: May 19, 2023Publication date: May 23, 2024Applicant: Tokyo Electron LimitedInventors: Scott LEFEVRE, Adam GILDEA, Satohiko HOSHINO, Sophia MADELONE, Yuji MIMURA
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Publication number: 20240071984Abstract: Devices and methods for forming semiconductor devices are disclosed. The semiconductor device can include a plurality of semiconductor wafers. The plurality of semiconductor wafers can have a dielectric bonding layer disposed thereupon. The dielectric bonding layers can be treated to increase a bonding energy with other semiconductor wafers. A wafer having a treatment applied to a bonding layer can be bonded to another wafer.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Applicant: Tokyo Electron LimitedInventors: Kandabara Tapily, Soo Doo Chae, Satohiko Hoshino, Hojin Kim, Adam Gildea
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Publication number: 20230075263Abstract: A semiconductor package is disclosed. The semiconductor package includes a first substrate including a first interconnect structure and a first bonding layer adjacent the first interconnect structure. The semiconductor package includes a second substrate including a second interconnect structure and a second bonding layer adjacent the second interconnect structure. The first bonding layer and second bonding layer each include a metal oxide.Type: ApplicationFiled: July 13, 2022Publication date: March 9, 2023Applicant: Tokyo Electron LimitedInventors: Soo Doo Chae, Sang Cheol Han, Hojin Kim, Kandabara Tapily, Satohiko Hoshino, Adam Gildea, Gerrit Leusink