Abstract: Hardware acceleration may be leveraged for performing secondary analysis. The hardware acceleration may be implemented by utilizing a plurality of field programmable gate arrays (FPGAs) installed on a device. Requests may be made from client processes for performing secondary analysis of sequencing data at a computing device. Each FPGA may be configured with an engine, or set of engines, configured to perform the secondary analysis to service the requests from client process. An FPGA may be configured with a plurality of engines configured for performing secondary analysis. The FPGA may be configured with a single instance comprising different types of engines for performing different types of secondary analysis. The FPGA may be configured with multiple instances of an engine, or set of engines, configured to perform the same or similar type of secondary analysis. The FPGA may share its resources with multiple client processes using one or more shared engines.

Abstract: A method and a system embodying the method for automatic application-specific instruction-set processor design and verification, comprising generating programming and simulation tools in accordance with application-specific instruction-set processor specifications automatically by an Electronic Design Automation tool; generating a reference model and a hardware description of the application-specific instruction-set processor in accordance with the application-specific instruction-set processor specifications automatically by the Electronic Design Automation tool; and verifying the hardware description against the reference model is disclosed.

Abstract: A method and a system embodying the method for automatic application-specific instruction-set processor design and verification, comprising generating programming and simulation tools in accordance with application-specific instruction-set processor specifications automatically by an Electronic Design Automation tool; generating a reference model and a hardware description of the application-specific instruction-set processor in accordance with the application-specific instruction-set processor specifications automatically by the Electronic Design Automation tool; and verifying the hardware description against the reference model is disclosed.

Abstract: A method and a system embodying the method for instruction translation, comprising providing a first finite state automaton; providing a second finite state automaton communicatively coupled with the first finite state automaton via a one-to-many relation; providing the instruction to be translated to one of the first or the second finite state automaton; and receiving a translated instruction from the other of the first or the second finite state automaton is disclosed.