Abstract: A computer system implements a memory unit, which includes first DRAM devices, second DRAM devices, a first memory controller, and a second memory controller. Each of the first DRAM devices have a first individual memory capacity and each of the second DRAM devices have a second individual memory capacity. The first memory controller is in signal communication with the first DRAM devices and the second memory controller is in signal communication with the second DRAM devices. Each of the first DRAM devices and the second DRAM devices are selectively operable as one of an active DRAM device to stare application data or a spare DRAM device reserved to receive the application data from the active DRAM devices to dynamically over-provision a total memory defined by a sum of the first and second individual memory capacities.

Abstract: A computer system implements a memory unit, which includes first DRAM devices, second DRAM devices, a first memory controller, and a second memory controller. Each of the first DRAM devices have a first individual memory capacity and each of the second DRAM devices have a second individual memory capacity. The first memory controller is in signal communication with the first DRAM devices and the second memory controller is in signal communication with the second DRAM devices. Each of the first DRAM devices and the second DRAM devices are selectively operable as one of an active DRAM device to stare application data or a spare DRAM device reserved to receive the application data from the active DRAM devices to dynamically over-provision a total memory defined by a sum of the first and second individual memory capacities.

Abstract: In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.

Abstract: A computer-implemented method, a computer program product, and a computer system for data flow management in a heterogeneous memory device. A media controller redirects traffic from first non-volatile memory (NVM) to second NVM, in response to an instantaneous temperature of the first NVM reaches a first predetermined temperature at which redirecting the traffic is started. The media controller throttles to reduce the traffic to the second NVM, in response to determining that the instantaneous temperature is higher than a second predetermined temperature at which throttling is started. The media controller redirects the traffic back to the first NVM, in response to determining that the instantaneous temperature is not higher than the second predetermined temperature and lower than a third predetermined temperature at which throttling is ended. The first NVM is thermally sensitive, while the second NVM is thermally tolerant.

Abstract: In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.

Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Abstract: A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with the L2 latch having a connected output monitored for a flip. A single L2 detect circuit exclusive OR (XOR) is connected to each L2 latch. An L2 detect circuit XOR tree includes an input connected to a true output of a respective L2 latch in the chain. An L2 clock (LCK) trigger circuit is connected to an output of the L2 detect circuit XOR tree and is shared across each of the plurality of L1 L2 latches for correcting bit flip errors.

Abstract: A computer-implemented method, according to one embodiment, includes: determining a current temperature associated with an intended storage location in memory for data in a write request, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.

Abstract: A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM), and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.

Abstract: A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.

Abstract: A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with the L2 latch having a connected output monitored for a flip. A single L2 detect circuit exclusive OR (XOR) is connected to each L2 latch. An L2 detect circuit XOR tree includes an input connected to a true output of a respective L2 latch in the chain. An L2 clock (LCK) trigger circuit is connected to an output of the L2 detect circuit XOR tree and is shared across each of the plurality of L1 L2 latches for correcting bit flip errors.

Abstract: A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.

Abstract: Embodiments include method, systems and computer program products for operating a dual in-line memory module with dedicated READ and WRITE ports. The computer-implemented method receiving, by a memory controller, one or more memory requests to access a one or more memory modules. The memory controller determines a memory request type for each of the one or more memory requests. The memory controller directs the one or more memory requests to a port of the memory controller dedicated to handle a memory request for an associated memory request type. The memory controller accesses at least a portion of the one or more memory modules via the dedicated port in which the one or more memory requests are directed.

Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: Aspects of the present disclosure relate to a memory module having a volatile memory, a high speed non-volatile memory, and a non-volatile memory. The memory module can allow write mirroring to the volatile memory and high speed non-volatile memory simultaneously. An I/O request is received. A determination is made whether the I/O request is a write or a read. In response to determining that the I/O request is a read, data included in the high speed non-volatile memory is transferred to the non-volatile memory. In response to determining that the I/O request is a write, at least one location to write data of the write is determined based on decoding bits of the write command. The data of the write can then be written to the at least one location.

Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Abstract: An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.

Abstract: A computer-implemented method for command-address-control calibration of a memory device includes starting, via a processor, a controller clock for the memory device, releasing, via the processor, a reset on the memory device, running, via the processor, a calibration pattern for calibrating the memory device by placing the memory device in calibration mode, where the calibration pattern is initiated prior to an initialization of the memory device, calibrating, via the processor, the memory device with a calibration setting based on the calibration pattern, and initializing the memory device based on the calibration setting.